R-3 Repository :: Browsing by Author "Karkooti, Marjan"

Browsing by Author "Karkooti, Marjan"

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Configurable LDPC Decoder Architecture for Regular and Irregular Codes
(Springer, 2008-11-01) Karkooti, Marjan; Radosavljevic, Predrag; Cavallaro, Joseph R.; Center for Multimedia Communication
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths −648, 1296, 1944-bits and code rates-1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
(2006-09-01) Karkooti, Marjan; Radosavljevic, Predrag; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
With the current trend of the increase in the data-rate requirements of wireless systems, there will be a huge need to increase their performance by utilizing more sophisticated channel coding algorithms. Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable these future wireless systems to grow with the demand. This paper presents a novel flexible architecture for irregular LDPC decoder that supports twelve combinations of code lengths - 648, 1296, 1944 bits - and code rates- 1/2, 2/3, 3/4, 5/6 - based on the IEEE 802.11n standard. All the codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. A prototype of the LDPC decoder has been implemented and tested on a Xilinx FPGA and has been synthesized for ASIC.
Distributed Decoding in Cooperative Communications
(IEEE, 2007-11-01) Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communication
In this paper, we present a novel relaying strategy called distributed and partial decoding. This strategy can be viewed as a variation of the decode and forward with the difference that the relay partially decodes the signal, re-transmits it to the destination, and the destination continues the decoding. By distributing the decoding process between the relay and the destination, the relay uses less processing power and less time. This is very suitable for practical applications in which relays are battery-operated (such as handsets) and do not want to use all their battery power on relaying the data of other users.
Distributed partial decoding in cooperative communication systems
(2009) Karkooti, Marjan; Cavallaro, Joseph R.
Increasing demand for wireless services is putting major pressure on network resources, which demands a new paradigm with a more efficient design. Recently, cooperative communications has emerged as a viable option for future wireless devices. Major improvements have been made in the theoretical analysis of cooperative communications and relay channels in recent years. But, most of the analyses have some simplifying assumptions that may not be valid in practice. These assumptions include using infinite-length block codes, zero processing delay, etc. This thesis considers cooperative communications from a practical point of view and identifies the benefits of cooperation when some of the theoretical assumptions are relaxed or changed. Several techniques are introduced to reduce the complexity of the system with minimal performance loss. We set up a framework for system design and show adaptability of our techniques to different scenarios. Our main focus is on the decode-and-forward relaying strategy with low density parity check (LDPC) codes. The thesis contributions in the field of cooperative communications fall into two main categories: algorithms and architectures. First, we focus on the complexity reduction in the algorithms and propose 'distributed partial decoding'. We demonstrate the benefits of partially decoding the codeword at the relay and distributing the decoding load between the relay and the destination. This results in major savings in terms of processing power and time at the relay with a very small loss in system performance. The architectural complexity and overhead of this scheme is much smaller than the original decode and forward strategy. The second contribution of this thesis is the design and implementation of a flexible LDPC decoder architecture that supports a family of LDPC with a variety of code rates and block lengths. This architecture is very suitable for cooperative environments where the cooperating pair and channel conditions and hence the code parameters are not known in advance. The third contribution relates to leveraging puncturing in cooperation. This work is the first to analyze cooperative communication with punctured LDPC codes. We propose structured puncturing patterns for quasi-cyclic LDPC codes and analyze the tradeoffs in designing good puncturing patterns for cooperative environments.
FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
(2005-11-01) Karkooti, Marjan; Cavallaro, Joseph R.; Dick, Chris; Center for Multimedia Communications (http://cmc.rice.edu/)
This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 by 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13 M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.
FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
(2005-10-01) Karkooti, Marjan; Cavallaro, Joseph R.; Dick, Chris; Center for Multimedia Communications (http://cmc.rice.edu/)
This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 Ã 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.
HIGH THROUGHPUT, PARALLEL, SCALABLE LDPC ENCODER/DECODER ARCHITECTURE FOR OFDM SYSTEMS
(IEEE, 2006-10-01) Sun, Yang; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communication
This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype architecture is being implemented on FPGA and tested over the air on our wireless OFDM testbed, which is a highly capable, scalable and extensible platform for advanced wireless research. The ASIC resource requirements of the decoder are reported and a trade-off between pipelined and non-pipelined implementation is described
High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices
(2006-09-01) Radosavljevic, Predrag; de Baynast, Alexandre; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
A high throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for the pre-determined set of code rates. The designed decoder achieves a data throughput of more than 1 Gb/s without sacrificing the error-correcting performance of capacity-approaching irregular block codes. The architecture is prototyped on an FPGA and synthesized for an ASIC design flow.
High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices
(2006-02-01) Radosavljevic, Predrag; de Baynast, Alexandre; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
High throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for pre-determined set of code rates. Designed decoder achieves data throughput of approximately 1 Gb/s without sacrificing error-correcting performance of capacity-approaching irregular block codes. The prototype architecture is implemented on FPGA.
Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis between Decoding Throughput and Area
(2006-09-01) Radosavljevic, Predrag; de Baynast, Alexandre; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths (up to 2.5K bits), several decoder solutions with different levels of processing parallelism are possible. Selection between these solutions is based on a threefold criterion:~hardware complexity, decoding throughput, and error-correcting performance. In this work, we determine multi-rate LDPC decoder architecture with the best tradeoff in terms of area size, error-correcting performance, and decoding throughput. The prototype architecture of optimal LDPC decoder is implemented on FPGA.
Semi-Parallel Architectures For Real-time LDPC Coding
(2004-05-01) Karkooti, Marjan; Center for Multimedia Communications (http://cmc.rice.edu/)
Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. ow Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area-time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3,6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes.
Semi-parallel architectures for real-time LDPC coding
(2004) Karkooti, Marjan; Cavallaro, Joseph R.
Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. Low Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3, 6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes.
Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding
(2004-04-01) Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
This paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of (3,6) LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps.
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
(IEEE, 2007-05-01) Sun, Yang; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communication
A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multirate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between 1/4 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR.

Browsing by Author "Karkooti, Marjan"

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