In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths (up to 2.5K bits), several decoder solutions with different levels of processing parallelism are possible. Selection between these solutions is based on a threefold criterion:~hardware complexity, decoding throughput, and error-correcting performance. In this work, we determine multi-rate LDPC decoder architecture with the best tradeoff in terms of area size, error-correcting performance, and decoding throughput. The prototype architecture of optimal LDPC decoder is implemented on FPGA.