Impulse sampler architecture and active clock cancellation architecture

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dc.contributor.assigneeRice Universityen_US
dc.contributor.publisherUnited States Patent and Trademark Officeen_US
dc.creatorAggrawal, Himanshuen_US
dc.creatorBabakhani, Aydinen_US
dc.date.accessioned2019-03-29T14:11:31Zen_US
dc.date.available2019-03-29T14:11:31Zen_US
dc.date.filed2017-02-25en_US
dc.date.issued2019-02-12en_US
dc.description.abstractA novel nonlinear impulse sampler is presented that provides a clock sharpening circuit, sampling stage, and post-sampling block. The clock sharpening circuit sharpens the incoming clock while acting as a buffer, and the sharpened clock is fed to the input of the sampling stage. The impulse sampling stage has two main transistors, where one transistor generates the impulse and the other transistor samples the input signal. Post-sampling block processes the sampled signal and acts as a sample and hold circuit. The architecture uses an ultrafast transmission-line based inductive peaking technique to turn on a high-speed sampling bipolar transistor for a few picoseconds. It is shown that the sampler can detect impulses as short as 100 psec or less.en_US
dc.digitization.specificationsThis patent information was downloaded from the US Patent and Trademark website (http://www.uspto.gov/) as image-PDFs. The PDFs were OCRed for access purposesen_US
dc.format.extent16en_US
dc.identifier.citationAggrawal, Himanshu and Babakhani, Aydin, "Impulse sampler architecture and active clock cancellation architecture." Patent US10204697B2. issued 2019-02-12. Retrieved from <a href="https://hdl.handle.net/1911/105262">https://hdl.handle.net/1911/105262</a>.en_US
dc.identifier.patentIDUS10204697B2en_US
dc.identifier.urihttps://hdl.handle.net/1911/105262en_US
dc.language.isoengen_US
dc.titleImpulse sampler architecture and active clock cancellation architectureen_US
dc.typeUtility patenten_US
dc.type.dcmiTexten_US
dc.type.genrepatentsen_US
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