Browsing by Author "de Baynast, Alexandre"

Now showing 1 - 20 of 22
  • Thumbnail Image
    Item
    Analysis of Decision-Feedback Based Broadband OFDM Systems
    (2005-11-01) de Baynast, Alexandre; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    In wireless communications, about 25% of the bandwidth is dedicated to training symbols for channel estimation. By using a semi-blind approach, the training sequence length can be reduced while improving performance. The principle is as follows: the detected symbols (hard decision) are fed back to the channel estimator in order to re-estimate the channel more accurately. However, semi-blind approach can significantly deteriorate the performance if the bit error rate is high. In this paper, we propose to determine analytically the minimum Signal to Noise Ratio (SNR) from which a semi-blind method starts to outperform a training sequence based only system.
  • Thumbnail Image
    Item
    ASIP Architecture Implementation of Channel Equalization Algorithms for MIMO Systems in WCDMA Downlink
    (2004-09-01) Radosavljevic, Predrag; Cavallaro, Joseph R.; de Baynast, Alexandre; Center for Multimedia Communications (http://cmc.rice.edu/)
    This paper presents a customized and flexible hardware implementation of linear iterative channel equalization algorithms for WCDMA downlink transmission in 3G wireless system with multiple transmit and receive antennas (MIMO system). Optimized (in terms of area and execution time) and power efficient Application Specific Instruction set Processors (ASIPs) based on Transport Triggered Architecture (TTA) are designed that can operate efficiently in slow and fast fading high scattering environments. The instruction set of TTA processors is extended with several user-defined operations specific for channel equalization algorithms that dramatically optimize the architecture solution for the physical layer of the mobile handset. The final results of presented design-space exploration method are the ASIP processors with low cost/performance ratio. Automatic software-hardware co-design flow for conversion of C application code into gate-level hardware design of ASIP architectures is also described. Implemented ASIP solutions achieve real time requirements for 3GPP wireless standard (1xEV-DV standard, in particular) with reasonable clock speed and power dissipation.
  • Thumbnail Image
    Item
    Bayesian Blind PARAFAC Recievers forDS-CDMA Systems
    (2003-10-01) de Baynast, Alexandre; Declercq, David; De Lathauwer, Lieven; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    In this paper an original Bayesian approach for blind detec-tion for Code Division Multiple Access (CDMA) Systems in presence of spatial diversity at the receiver is developed. In the noiseless context, the blind detection/identification problem relies on the canonical decomposition (also re-ferred as Parallel Factor analysis [Sidiropoulos, IEEE SP 00], PARAFAC. The author in [Bro,INCINC 96] pro-poses a suboptimal solution in least-squares sense. How-ever, poor performance are obtained in presence of high noise level. The recently emerged Markov chain Monte Carlo (MCMC) signal processing method provide a novel paradigm for tackling this problem. Simulation results are presented to demonstrate the effectiveness of this method.
  • Thumbnail Image
    Item
    Blind PARAFAC Receivers for Multiple Access-Multiple Antenna Systems
    (2003-10-01) de Baynast, Alexandre; De Lathauwer, Lieven; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    In this paper, we present a new blind receiver for multiple access channel with multiple transmit antennas per user and multiple receive antennas (MIMO channel). After being multiplied by a spreading sequence, each user s data is split into Nt streams that are simultaneously transmitted using Nt transmit antennas. The received signal at each receive antenna is a linear superposition of the Nt transmitted signals of the Nu users perturbed by noise. We propose a new blind detection/identification algorithm under the assumption that the fading is slow and frequency non-selective. This algorithm relies on a generalization of parallel factor analysis (PARAFAC analysis, [Kruskal, Lin. Alg. Appl. 77, Sidiropoulos, Tr. on Sig. Proc. 00]): we show that a generalized canonical decomposition (CANDECOMP) of the 3D data tensor is unique under mild assumptions without noise. Neither algebraic orthogonality nor independence between sources is needed for uniqueness of the decomposition. By performing this decomposi-tion, in rank-(Nt,Nt,1) terms, we are able to retrieve the three sets of parameters: the symbols, the channel fading coefficients (including the antenna gains) and the spreading sequences. In a noisy context, we propose a simple algorithm of the alternating least squares (ALS) type, which yields a performance close to the linear minimum mean square error (LMMSE) receiver which requires knowledge of the channel and spreading sequences.
  • Thumbnail Image
    Item
    Chip level LMMSE Equalization for Downlink MIMO CDMA in fast fading environments
    (2004-11-01) de Baynast, Alexandre; Radosavljevic, Predrag; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    In this paper, we consider linear MMSE equalization for wireless downlink transmission with multiple transmit and receive antennas in fast fading environment. We propose a new algorithm based on conjugate-gradient algorithm with enhanced channel estimation. In order to be robust to the channel variations, the channel coefficients are estimated by using a weighted sliding window. Two methods to determine optimal weights with respect to the Doppler frequency are proposed. The algorithm has been tested in fast fading environment (Vehicular A for a velocity for the mobile station of 120 km/h). We show by simulations that good performance are obtained in correlated fast fading environment with reasonable complexity. Moreover, this method outperforms approaches based on forgetting factor, basic sliding window and LMS.
  • Thumbnail Image
    Item
    Half-Duplex Estimate-and-Forward Relaying: Bounds and Code Design
    (2006-07-01) Chakrabarti, Arnab; de Baynast, Alexandre; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    We propose a coding scheme for half-duplex estimate-and-forward relaying. Our first contribution is to present an achievable rate for the estimate-and-forward protocol. We also derive the achievable rate for the special case of a Gaussian half-duplex relay channel. Guided by the information theoretic coding scheme for the aforementioned achievable rate, we propose a practical coding scheme. The proposed coding scheme incorporates several design choices to reduce receiver complexity without compromising performance. Binary LDPC codes are used in the source broadcast phase. Estimation is performed by scalar quantization of the received signal at the relay. Finally, a procedure similar to maximal ratio combining is used to aggregate direct and relayed signals at the destination. An important practical advantage of our scheme is that it does not require symbol level source-relay synchronization. The codes outperform direct and two-hop channel capacities, as well as decode-and-forward relaying when the relay-destination link is strong.
  • Thumbnail Image
    Item
    Half-Duplex Estimate-and-Forward Relaying:Bounds and Code Design
    (2006-01-01) Chakrabarti, Arnab; de Baynast, Alexandre; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    We propose a coding scheme for half-duplex estimate-and-forward relaying. Our first contribution is to present an achievable rate for the estimate-and-forward protocol. We also derive the achievable rate for the special case of a Gaussian half-duplex relay channel. Guided by the information theoretic coding scheme for the aforementioned achievable rate, we propose a practical coding scheme. The proposed coding scheme incorporates several design choices to reduce receiver complexity without compromising performance. Binary LDPC codes are used in the source broadcast phase. Estimation is performed by scalar quantization of the received signal at the relay. Finally, a procedure similar to maximal ratio combining is used to aggregate direct and relayed signals at the destination. An important practical advantage of our scheme is that it does not require symbol level source-relay synchronization. The codes outperform direct and two-hop channel capacities, as well as decode-and-forward relaying when the relay-destination link is strong.
  • Thumbnail Image
    Item
    High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices
    (2006-09-01) Radosavljevic, Predrag; de Baynast, Alexandre; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    A high throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for the pre-determined set of code rates. The designed decoder achieves a data throughput of more than 1 Gb/s without sacrificing the error-correcting performance of capacity-approaching irregular block codes. The architecture is prototyped on an FPGA and synthesized for an ASIC design flow.
  • Thumbnail Image
    Item
    High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices
    (2006-02-01) Radosavljevic, Predrag; de Baynast, Alexandre; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    High throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for pre-determined set of code rates. Designed decoder achieves data throughput of approximately 1 Gb/s without sacrificing error-correcting performance of capacity-approaching irregular block codes. The prototype architecture is implemented on FPGA.
  • Thumbnail Image
    Item
    Implementation of Iterative Channel Equalization for MIMO Systems in WCDMA Downlink
    (2003-10-20) Radosavljevic, Predrag; Cavallaro, Joseph R.; de Baynast, Alexandre; Center for Multimedia Communications (http://cmc.rice.edu/)
    In downlink transmission, channel multipaths destroy the orthogonality between users causing Multiple Access Interference (MAI). In order to restore the orthogonality between the users, chip-level channel equalization based on the iterative conjugate-gradient (CG) algorithm has been proposed in [Heikkilla '02]. We extend this approach to the multiple transmit antenna case and propose 16-bit fixed point implementation. Simulations show the robustness of the fixed point implementation of the proposed algorithm. Moreover, this approach outperforms RAKE receiver in all cases.
  • Thumbnail Image
    Item
    LDPC Code Design for Half-Duplex Decode-and-Forward Relaying
    (2005-09-01) Chakrabarti, Arnab; de Baynast, Alexandre; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    We propose LDPC code designs for the half-duplex relay channel. Our designs mimic the information theoretic random coding scheme for decode-and-forward relaying. An important advantage of our scheme is that it is built entirely of single-user codes that can be decoded by belief propagation. The optimization of relay LDPC code profiles presents unique challenges, which are met by using the density evolution algorithm with additional constraints for relaying. To speed up our optimization, we use a Gaussian approximation of density evolution that converts the infinite dimensional code profile optimization into a simple linear programming problem. The thresholds of the discovered relay code profiles are within 0.4 dB of the achievable lower bound for decode-and-forward relaying.
  • Thumbnail Image
    Item
    LDPC Code Design for OFDM Channel: Graph Connectivity and Information Bits Positioning
    (2005-07-01) de Baynast, Alexandre; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    We present an optimized channel coding scheme for OFDM transmission. In the future wireless standards such IEEE 802.11n, frame error rates (FER) as low as 0.0001 are targeting. Irregular LDPC codes have excellent performance at moderate computational complexity: they are strong candidates for channel coding in such systems. In the context of an OFDM transmission, the authors in [Mannoni, 2002] proposed to optimize the graph connectivity of the irregular LDPC code accordingly to the channel spectrum. However, their codes did not have good performance for a FER range of 0.001 - 0.0001. In this paper, we propose to optimize the LDPC code in two steps: first, we optimize the graph connectivity in order to get a minimum operational average SNR and therefore excellent FER; then we optimize the information bits placement accordingly to the channel. By simulation, we show that our approach provides substantial performance gain in term of FER over the existing methods (1 dB or more for FER equal to 10e-4.
  • Thumbnail Image
    Item
    LDPC Code Design for Relay Channel in Time-Division mode
    (2006-06-01) de Baynast, Alexandre; Chakrabarti, Arnab; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    We address the problem of LDPC code design for relay channel in time-division mode based on a distributed strategy: In the first time slot, the source transmits part of the codeword. The relay and the destination receive it but only the relay can decode it. In the second time slot, the relay transmits the additional redundant bits to the destination. The destination is able to decode the transmitted codeword based on the data received in both time slots. The asymptotic performance of the LDPC codes that we designed are as close as 0.6 decibel from the theoretical limit.
  • Thumbnail Image
    Item
    LDPC Code-Design for the Relay Channel
    (2006-06-01) Chakrabarti, Arnab; de Baynast, Alexandre; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    We propose LDPC code designs for the half-duplex relay channel. Our designs are derived from the information theoretic random coding scheme for decode-and-forward relaying. An important advantage of our scheme is that it is built entirely of single-user codes. The optimization of relay LDPC code profiles presents unique challenges, which are met by modifying the density evolution algorithm by introducing additional constraints for relaying. To speed up optimization, we use a Gaussian approximation of density evolution that converts the infinite dimensional code profile optimization into a simple linear programming problem. The thresholds of the discovered relay code profiles are a fraction of a dB from the achievable lower bound for decode-and-forward relaying.
  • Thumbnail Image
    Item
    LDPC Code-Design for the Relay Channel
    (2006-02-01) Chakrabarti, Arnab; de Baynast, Alexandre; Sabharwal, Ashutosh; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)
    We propose LDPC code designs for the half-duplex relay channel. Our designs are derived from the information theoretic random coding scheme for decode-and-forward relaying. An important advantage of our scheme is that it is built entirely of single-user codes. The optimization of relay LDPC code profiles presents unique challenges, which are met by modifying the density evolution algorithm by introducing additional constraints for relaying. To speed up optimization, we use a Gaussian approximation of density evolution that converts the infinite dimensional code profile optimization into a simple linear programming problem. The thresholds of the discovered relay code profiles are a fraction of a dB from the achievable lower bound for decode-and-forward relaying.
  • Thumbnail Image
    Item
    Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis between Decoding Throughput and Area
    (2006-09-01) Radosavljevic, Predrag; de Baynast, Alexandre; Karkooti, Marjan; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    In order to achieve high decoding throughput (hundreds of MBits/sec and above) for multiple code rates and moderate codeword lengths (up to 2.5K bits), several decoder solutions with different levels of processing parallelism are possible. Selection between these solutions is based on a threefold criterion:~hardware complexity, decoding throughput, and error-correcting performance. In this work, we determine multi-rate LDPC decoder architecture with the best tradeoff in terms of area size, error-correcting performance, and decoding throughput. The prototype architecture of optimal LDPC decoder is implemented on FPGA.
  • Thumbnail Image
    Item
    On Turbo-Schedules for LDPC Decoding
    (2006-05-01) de Baynast, Alexandre; Radosavljevic, Predrag; Sabharwal, Ashutosh; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    The convergence rate of LDPC decoding is comparatively slower than turbo code decoding: 25 LDPC iterations versus 8-10 iterations for turbo codes. Recently, Mansour proposed a â turbo-scheduleâ to improve the convergence rate of LDPC decoders. In this letter, we first extend the turbo-scheduling principle to the check messages. Second, we show analytically that the convergence rate of both turbo-schedules is about twice as fast as the standard message passing algorithm for most LDPC codes.
  • Thumbnail Image
    Item
    Optimized Message Passing Schedules for LDPC Decoding
    (2005-11-01) Radosavljevic, Predrag; de Baynast, Alexandre; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    The major drawback of the LDPC codes versus the turbo-codes is their comparative low convergence speed: 25-30 iterations vs. 8-10 iterations for turbo-codes. Recently, Hocevar showed by simulations that the convergence rate of the LDPC decoder can be accelerated by exploiting a â turbo-schedulingâ applied on the bit-node messages (rows of the parity check matrix). In this paper, we show analytically that the convergence rate for this type of scheduling is about two times increased for most of the regular LDPC codes. Second we prove that â turbo-schedulingâ applied on the rows of the parity check matrix is identical belief propagation algorithm as standard message passing algorithm. Furthermore, we propose two new message passing schedules: 1) a turbo-scheduling is applied on the checknode messages (columns of the parity check matrix); 2) a hybrid version of both previous schedules where the turbo-effect is applied on both check-nodes and bit-nodes. Frame error rate simulations validate the effectiveness of the proposed schedules.
  • Thumbnail Image
    Item
    Optimized Message Passing Schedules for LDPC Decoding
    (2005-11-01) Radosavljevic, Predrag; de Baynast, Alexandre; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    The major drawback of the LDPC codes versus the turbo-codes is their comparative low convergence speed: 25-30 iterations vs. 8-10 iterations for turbo-codes. Recently, Hocevar showed by simulations that the convergence rate of the LDPC decoder can be accelerated by exploiting a â turbo-schedulingâ applied on the bit-node messages (rows of the parity check matrix). In this paper, we show analytically that the convergence rate for this type of scheduling is about two times increased for most of the regular LDPC codes. Second we prove that â turbo-schedulingâ applied on the rows of the parity check matrix is identical belief propagation algorithm as standard message passing algorithm. Furthermore, we propose two new message passing schedules: 1) a turbo-scheduling is applied on the checknode messages (columns of the parity check matrix); 2) a hybrid version of both previous schedules where the turbo-effect is applied on both check-nodes and bit-nodes. Frame error rate simulations validate the effectiveness of the proposed schedules.
  • Thumbnail Image
    Item
    Performance of Multi Binary Turbo-Codes on Nakagami Flat Fading Channels
    (2006-05-01) de Baynast, Alexandre; Center for Multimedia Communications (http://cmc.rice.edu/)
    In this paper, performance in terms of Bit Error Rate (BER) and Frame Error Rate (FER) of multi binary turbo codes (MBTC) over Nakagami frequency nonselective fading channels are presented. The proposed MBTCs consist of the parallel concatenation of two identical 2/3-rate recursive systematic, convolutional (RSC) double binary codes. We choose to model the channel fading with Nakagami-m distribution since it fits well to the empirical fading data of the current wireless transmission systems. The simulation results show that the MBTCs outperform the classical turbo codes for low-targeted FER (around 10e-4) since their error-floor is negligible.