Browsing by Author "Xu, Gang"
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Item Implementation Issues of Multiuser Detection in CDMA Communication Systems(1999-05-20) Xu, Gang; Center for Multimedia Communications (http://cmc.rice.edu/)Multistage detectors have been accepted in designs for next generation CDMA base stations because they are less complex than some other multiuser detectors. In this thesis, we propose a differencing method to further reduce complexity. It achieves both high performance in the interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. We recode the estimation bits, mapping from ±1 to 0 and ±2. Bypassing all the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. The system delay of a five-stage detector will be reduced by 75% with a satisfactory bit error rate. We also investigated fixed-point implementation issues and implemented this algorithm in a real-time system using both TI's TMS320C62 DSP and ASICs.Item Implementation issues of multiuser detection in CDMA communication systems(1999) Xu, Gang; Cavallaro, Joseph R.Multistage detectors have been accepted in designs for next generation CDMA base stations because they are less complex than some other multiuser detectors. In this thesis, we propose a differencing method to further reduce complexity. It achieves both high performance in the interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. We recode the estimation bits, mapping from $\pm1$ to 0 and $\pm2$. Bypassing all the zero terms saves computations. Multiplication by $\pm2$ can be easily implemented in hardware as arithmetic shifts. The system delay of a five-stage detector will be reduced by 75% with a satisfactory bit error rate. We also investigated fixed-point implementation issues and implemented this algorithm in a real-time system using both TI's TMS320C62 DSP and ASICs.Item Implementation of Channel Estimation and Multiuser Detection Algorithms for W-CDMA on Digital Signal Processors(1999-08-20) Rajagopal, Sridhar; Xu, Gang; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)Proposed algorithms for Third Generation W-CDMA communication systems have extremely high performance requirements. In this paper, we study the implementation issues involved for one of the proposed multiuser channel estimation and detection algorithms for base-stations in the uplink using TI's TMS320C6x DSP Evaluation Modules(EVM). It was found that these proposed algorithms for multiuser channel estimation and detection have different processing and precision requirements. While the detector can be implemented using the C6201 16-bit fixed point DSP, the proposed channel estimation algorithm may be more suitable for a oating point implementation using the C6701 floating point DSP. We study the effects of the specialized approximate instructions available on the C6701 DSP on channel estimation. Then, the advantage of multistep optimizations and use of assembly code is studied for both the algorithms. Memory issues involved in the implementation of these algorithms is also investigated. It was found that the data memory requirements for channel estimation for the chosen system parameters necessitates the use of external memory while the multistage detection algorithm could be placed in the available internal data memory. We finally discuss the current and future trends of DSPs and their utilization for such wireless communication applications.Item Rapid Scheduling of Efficient FPGA Architectures for Next-Generation HSDPA Wireless System Using Precision C Synthesizer(2003-06-20) Guo, Yuanbin; McCain, Dennis; Xu, Gang; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architec-tures are scheduled rapidly with specific hardware re-source/timing/architecture constraints from C/C++ level modeling by allocating the usage of functional units and real-time requirements. Using this methodology, a system-on-chip architecture for the next-generation CDMA system, i.e., HSDPA system, is prototyped rapidly. Advanced algo-rithms including chip-level equalizer, turbo codec and clock tracking, frequency offset compensation, are scheduled with Precesion C. A relatively more area/timing efficient RTL architecture is generated automatically and integrated with other design blocks in HDL designer, then implemented efficiently in Xilinx FPGAs. This new design flow demon-strates productivity improvement of 2X for typical wireless communication algorithms and reduces the risk of product development dramatically.Item Real-time implementation of the multistage detector for next generation Wideband CDMA systems(1999-07-20) Xu, Gang; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)The multistage detection algorithm has been widely accepted as an exective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time implementation of this detection algorithm in the uplink system, where we have achieved both high performance in the interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. We recode the estimation bits, mapping from ±1 to 0 and ±2. Bypassing all the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. The system delay ofa three-stage detector can be reduced by half with satisfactory bit error rate. We also propose a VLSI implementation of this algorithm that has the potential of real-time performance. The detector handling up to eight users with 12-bit fixed point precision was fabricated using a 1.2 um CMOS technology.Item VLSI implementation of the multistage detector for next generation wideband CDMA receivers(Kluwer Academic Publishers, 2002-03-20) Xu, Gang; Rajagopal, Sridhar; Cavallaro, Joseph R.; Aazhang, Behnaam; Center for Multimedia Communications (http://cmc.rice.edu/)The multistage detection algorithm has been proposed as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stations. In this paper, we propose a real-time VLSI implementation of this detection algorithm in the uplink system, where we have achieved both high performance in interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. Under the assumption of BPSK modulation, the differences between the bit estimates from consecutive stages are 0 and ±2. Bypassing the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. However, the convergence of the algorithm is dependent on the number of users, the interference and the signal to noise ratio and hence, the detection has a variable execution time. By using just two stages of the differencing detector, we achieve predictable execution time with performance equivalent to at least eight stages of the regular multistage detector. A VLSI implementation of the differencing multistage detector is built to demonstrate the computational savings and the real-time performance potential. The detector, handling up to eight users with 12-bit fixed point precision, was fabricated using a 1.2 um CMOS technology and can process 190 Kbps/user for 8 users.