Multistage detectors have been accepted in designs for next generation CDMA base stations because they are less complex than some other multiuser detectors. In this thesis, we propose a differencing method to further reduce complexity. It achieves both high performance in the interference cancellation and computational efficiency. When interference cancellation converges, the difference of the detection vectors between two consecutive stages is mostly zero. We recode the estimation bits, mapping from ±1 to 0 and ±2. Bypassing all the zero terms saves computations. Multiplication by ±2 can be easily implemented in hardware as arithmetic shifts. The system delay of a five-stage detector will be reduced by 75% with a satisfactory bit error rate. We also investigated fixed-point implementation issues and implemented this algorithm in a real-time system using both TI's TMS320C62 DSP and ASICs.