R-3 Repository :: Browsing by Author "Jump, J. Robert"

Browsing by Author "Jump, J. Robert"

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A categorical model for data structures
(1973) Meyer, Susan Conry; Jump, J. Robert
In this thesis we consider the problem of modeling data structures. A model based on category theory is proposed in which both the static and dynamic characteristics of data structures can be represented. Data structures are modeled by categories and their dynamic characteristics by functors between these categories. Hierarchical data structures are considered, and examples are given of several common types of information structures and their description within this model. The categorical model for data structures is employed in studying those properties of data structures which are due to their structure alone. This is done by considering the functors between the representations of different data structures in order to study the relationships between them. An indication of when one data structure can be realized in another is given and the class of realizations of a data structure D in another data structure D is characterized. Finally, a sufficient condition is given for the realization of one class of data structures in another.
A loop structured technique for the control of a multiprocessing system
(1975) Bain, William Lamar; Jump, J. Robert
A method for routing control information to and from the processors in a multiprocessing system is presented and analyzed. The technique requires the construction of two sets of data registers connected in the form of closed loops. Every processor is interfaced to one register on each loop through which data is propagated in a parallel manner and at a constant rate (as controlled by a system clock). A system controller introduces data words called "packets" onto the "input" loop for distribution to available processors. The packets contain information sufficient for the initiation of concurrent tasks. The processors input these packets, execute tasks as directed, and generate similar packets which signify task completion. The latter packets are deposited on the "output" loop by the processors for return to the system controller. The analysis reveals that under appropriate restrictions (namely, a large supply of tasks, a fixed task execution time, and the efficient handling of packets by the system controller), the scheme makes effective use of processing resources. The throughput of tasks increases linearly with the addition of processors until the number of processors, n, is equal to the ratio of task execution time to system clock time, p, after which it remains fixed as more processors are added. The overhead required to route control information through the system decreases as 1/n until n equals p, whereupon it increases linearly for larger n. A simulator, used to verify the analysis and extend same to more general systems, is also described. It shows that as restrictions are lifted, the loop structured technique continues to be a viable scheme for the control of a multiprocessor, especially in applications in which its simplicity and modularity are advantageous.
A microprocessor system designed for use in the laboratory
(1988) Waites, Nigel Derek; Jump, J. Robert
The goal of the project was to design a low cost microprocessor system for laboratory use. A general purpose microprocessor board was conceived that could be used in a card type system or with the special purpose mother board, which would give the microprocessor board protection from the students, and which would conveniently distribute signals through breadboard terminals for connection to external circuitry. This thesis focuses on the development of the system, both in terms of hardware and software. The project's goals have all been achieved; forty microprocessor systems were built, and they are presently being used in the laboratory. The bundled hardware and software package gives the user access to the equivalent of a small development system that provides a user-friendly environment, at a fraction of the cost of any commercially available development system.
A programmable cellular array
(1971) Fritsche, Dennis Ray; Jump, J. Robert
A programmable cellular array is investigated in this thesis. Each cell in the array is a multi-state network containing combinational logic and a data storage element. The function performed by a cell is determined by the state of the cell and by inputs from neighboring cells. This method of choosing the cell's function allows any combination of cell states in a row or a column. Also, utilization of signals from neighboring cells allows internally generated (as well as external) signals to control a cell. The array is utilized by first programming it to perform several operations and then applying microinstructions which cause the operations to be executed. (A program is a specification of the state of the cells in the array.) The microinstructions contain both data and control information so that all inputs are to the top of the array. This feature reduces the number of external pins to the array. The array can be programmed to operate as an arithmetic processor capable of performing several arithmetic operations. This ability is demonstrated by the implementation of algorithms to perform binary addition, subtraction, multiplication, and division. The array can be programmed to perform other useful operations including conversion between BCD and binary representations, double-precision addition, decimal addition and subtraction, and permutation of variables.
A study of structured Free Choice Petri nets
(1975) Jotwani, Naresh Dhanraj; Jump, J. Robert
A sub-class of the class of Free Choice Petri nets the class of Acyclic Free Choice Petri nets (AFCP nets) is first defined. After some of the properties of AFCP nets have been examined, a definition is made of Structured AFCP nets, i.e. AFCP nets which can be obtained by repeated top-down expansion, referred to as DU-Expansion, of an Acyclic Marked Graph (AMG). It is shown that an AFCP net is Structured if and only if it yields an AMG on repeated application to it of the process of DU-Reduction -- the converse of the process of DU-Expansion. An asynchronous control scheme, the Acyclic Control Structure (ACS), is then defined around AFCP nets. Definitions are made of the external behavior of the ACS and of the simulation of one ACS by another. A Structure Algorithm is presented which, given an ACS A, finds ACS Ag which simulates A and which is known to contain at least one subnet that can be collapsed by DU-Reduction. Theorems are presented proving the correctness of the algorithm. Finally, it is shown that any ACS can be simulated by a Structured ACS -- one built around a Structured AFCP net.
A variable character set printer
(1971) Bohlmann, Rodney John; Jump, J. Robert
Because of the number of different computer languages available today, a line printer which is capable of printing any character is desirable. This thesis presents a printing mechanism, and a controller for that mechanism, which together realize such a printer. The result is a printer with 512 completely variable characters, both in terms of the characters' appearance as well as their codes.
Algebraic models for asynchronous control structures
(1972) Thiagarajan, P. S; Jump, J. Robert
The study of asynchronous control structures used for enforcing the coordination required to carry out an activity that exhibits concurrency is of considerable interest and importance. A large class of these control structures can be adequately and concisely described by Petri-nets. The Petri-net, being a graphical model, promises to be a powerful tool in the design of such control structures. However, precisely because it is a graphical model, the Petri-net is not amenable to elegant mathematical analysis. Hence it is difficult to find answers to significant questions regarding the structure and behavior of asynchronous control structures if their sole available descriptions are in the form of Petri-nets. For this reason, the problem of formulating valid algebraic models for the above-mentioned class of control structures is studied. In particular, attention is confined to those control structures that can be described by marked graphs, which are a restricted type of Petrinets. Two algebraic models called the C-D model and the Poset model are formulated and their validity is established. Both these models represent the control structure under study by specifying the cause-effect relationship imposed by the control structure on the flow of signals that are associated with it. Finally, as an example of the application of these two models, a simple scheme for realizing marked-graph-describable asynchronous control structures is demonstrated.
An efficient implementation of Batcher's odd-even merge algorithm and its application in parallel sorting schemes
(1981) Kumar, Manoj; Hirschberg, Daniel S.; Sinclair, James B.; Jump, J. Robert
An algorithm is presented to merge two subfiles of size n/2 each, stored in the left and the right halves of a linearly-connected processor array, in 3n/2 route steps and log n compare-exchange steps. This algorithm is extended to merge two horizontally adjacent subfiles of size mXn/2 each, stored in an mXn mesh-connected processor array in row-major order, in m+2n route steps and log mn compare-exchange steps. These algorithms are faster than their counterparts proposed so far. Next, an algorithm is presented to merge two vertically aligned subfiles, stored in a mesh-connected processor array in row-major order. Finally, a sorting scheme is proposed that requires lln route steps and 2 log n compare-exchange steps to sort n elements stored in an nXn mesh-connected processor array. The previous best sorting algorithm requires 14 n route steps ( for practical values of n, 4 < n 512 ).
An Experimental Computer Network to Support Numerical Computation
(1982-03) Cartwright, Robert; Dennis, J.E. Jr.; Jump, J. Robert; Kennedy, Ken
The Computer Science faculty at Rice University proposes to design and implement an experimental distributed computing system to support numerical computation. Although local networks of single user machines have already been proven for many nonnumerical applications, the concept has yet to be tried in the context of numerical program development and execution. The Rice Numerical Network, or R^n, will consist of approximately 24 single-user numerical machines equipped with high-resolution bit-mapped screens, a 32-bit central processor, and vector floating point hardware. It will also include several specialized server nodes supporting a high-performance vector floating point processor and various peripheral devices including a gateway to the SCnet communications network linking the nation's major computer science research centers. The new facility will support a coherent research program in software systems, computer architecture, and quality numerical software, directed at creating a modern reactive environment for numerical computation. Despite stiff competition from industry and other universities, Rice University has recently assembled the nucleus of computer science faculty required to develop an innovative distributed computing system supporting vector numerical computation and to evaluate its utility as a tool for solving important scientific problems.
CSIM: an efficient implementation of a discrete-event simulator
(1985) Covington, Richard Glenn; Jump, J. Robert; Sinclair, James B.; Briggs, Faye A.
We discuss the design and efficient implementation of the Rice C Simulation Package (CSIM), a software tool, written in C, and designed to work compatibly with the standard C compiler. The tool provides support for discrete-event or process-interaction simulation, especially for digital logic and queuing theoretic models. We first discuss the existing modeling formalism necessary to abstract a discrete-event model from a real system. We then introduce a set of primitives which are sufficient for preparing an algorithmic specification of the abstract model. Finally, we report on the successful realization of the primitives, discussing or clarifying existing modeling methodology and establishing new methodology when necessary. We also describe the implementation of a recently proposed efficient event list algorithm (the TL algorithm), and present a study of its complexity.
Data flow program reduction
(1978) Dias, Daniel M.; Jump, J. Robert
In data flow programs, instructions execute when their operands become available. The arrival of data thus acts as the control as well and leads to models with a single graph representing the data and the control flow. In this thesis, we transform a data flow model to one with a separate data and control flow. This is motivated by 'reductions' that can be carried out on the transformed model and by the ease of implementing such models by conventional techinques. Data flow models are networks consisting of operators and control nodes connected by data paths. The operator nodes carry out a functional operation on the input data while the control nodes route the data correctly. In directly implementing a data flow program, 'copy' operations are required for the control nodes. We specify conditions which allow the removal of these copy operations in the transformed model. The problem is significant since the control nodes often make up more than half of the data flow program The control flow is then simplified and it is demonstrated that this simplification can lead to an increase in parallelism. Finally, the implications of the analysis to extant architectures is considered and it is shown how the results motivate a separation of the data and the control flow in implementing a data flow processor.
Delay line synthesis of sequential machines
(1970) Marathe, Shreehari Ganesh; Jump, J. Robert
This thesis deals with the problem of realizing state sequential machines with delay line networks which are a special case of shift register networks. A formal definition of delay line networks is given with an algebraic model in terms of the following four parameters: the input set I, the number of delay lines m, the length of delay line 1, and the logic function f. With the help of this model, the concept of a state being in a cycle of length c is defined and it is shown that such a state is periodic with period c. The following result concerning the periodicity of doubly periodic finite sequence is proved: if a finite sequence is periodic with periods u and v and if the length of the sequence is greater than or equal to u+v-g where g is the greatest common division of u and v, then the sequence is periodic with period g. These results are related by proving that if a state is in two cycles of length u and v, then the length of the delay line must be less than u+v-g. A method is developed to derive bounds for the length and number of delay lines for a delay line network to realize a given machine. A constructive synthesis algorithm is given to find a delay line realisation of given machine in the above bounds if such an assignment exists. This algorithm utilizes a state assignment procedure to assign the states of a given machine to the states of a specific delay line network.
Dynamic memory interconnections for rapid access
(1981) Iyer, Balakrishna R.; Sinclair, James B.; Hirschberg, Daniel S.; Jump, J. Robert
A dynamic memory is a storage facility for fixed-size data items. The memory is comprised of cells, each cell capable of storing one datum. Data paths between cells are provided by a memory interconnection network. Each cell is directly connected to only a small number of cells. At every clock pulse, data items migrate from cell to cell via the data paths. The memory cells may be divided into several groups. A control mechanism provides each group of memory cells with a control signal. This control signal determines the data paths to be taken by data items contained in all cells within the group. Many dynamic memory organizations have been proposed. These exhibit trade-offs between the time to access a datum randomly and the time to access serially a block of logically contiguous data. The access times for these organizations are derived where necessary and compared. A new organization called the deck memory organization is proposed. Access times for the deck are determined and compared with access times derived for other organizations.
Efficient methods for cache performance prediction
(1989) Dwarkadas, Sandhya; Jump, J. Robert; Sinclair, James B.
The goal of our work is to develop techniques that accurately and efficiently simulate the behavior of computer systems with cache memories. This thesis describes the design, analysis, and validation of three such methods of cache performance prediction. Execution-driven simulation is a technique that avoids the high overhead associated with instruction-level simulation while retaining most of the accuracy of that technique. We have extended the execution-driven paradigm to develop a time and space-efficient technique for address trace generation and cache simulation, as well as to provide estimates of overall execution time. The second method that we have developed is an analytical model for the prediction of cache miss ratios using single-process traces. Finally, a simple and efficient estimative simulation technique based on the analytical model and the execution-driven paradigm has been outlined. This approach is demonstrated in the simulation of cache-based multiprocessor systems in conjunction with the Rice Parallel Processing Testbed, which simulates concurrent algorithms on parallel architectures.
Efficient simulation and utilization of a parallel digital signal processing architecture
(1989) Foundoulis, William James; Jump, J. Robert; Sinclair, James B.
In this study we discuss the development and validation of an efficient and accurate execution-driven simulation of the Texas Instruments Odyssey System, a parallel configuration of digital signal processors. We also evaluate the performance of a high-level parallel programming interface, Odyssey Concurrent C, designed to effectively utilize the parallelism available in the Odyssey architecture. Parallel versions of three dissimilar algorithms--merge sort, 2-dimensional convolution, and successive over-relaxation--have been run on both the Odyssey and the simulator. Quantitative differences between performance results obtained on the Odyssey and those predicted by simulation are enumerated, and shown to validate the accuracy of the execution-driven approach. The simulation is also shown to be efficient relative to the degree of accuracy obtainable. Finally, the Odyssey Concurrent C utilities are shown to provide a flexible and effective mechanism for managing parallelism in the Odyssey environment.
Efficient simulation of interconnection networks
(1993) Lakshmanamurthy, Sridhar; Jump, J. Robert
This thesis presents a modular, general-purpose interconnection network simulator called NETSIM developed as an extension to YACSIM, a C-language based process-oriented discrete event simulator. NETSIM is capable of simulating a wide range of switch architectures and network topologies. A NETSIM model can be simulated in a stand-alone mode with the network traffic generated by stochastic processes, or it can be used as an integral part of PARCSIM in an execution-driven simulation environment. This work emphasizes simulating complex switching schemes like wormhole routing efficiently. A detailed model for wormhole routing is implemented using two different techniques, and their relative advantages are evaluated. The thesis also presents four approximate models for simulating wormhole routing and evaluates the tradeoff between speedup and the accuracy of the approximate models. This thesis also develops a validation model for the iPSC/860 interconnection network using the NETSIM primitives, and evaluates the accuracy of the model in predicting the message latencies for the iPSC/860 system.
Efficient simulation of simple instruction set array processors
(1990) Dawkins, William P.; Jump, J. Robert
Simple instruction set array processors are groups of regularly connected processors with small instruction sets and local memories. The processors are augmented by built-in communication instructions. Because of the complexity of implementing these systems, a method of simulating simple instruction set array processors is developed for evaluating the performance of architectures and algorithms. This technique, called hybrid instruction-level/execution-driven simulation, uses a translator-profiler to extract timing information from a program written in a simple instruction set processor's (SISP) assembly language. The translator-profiler converts the assembly language program and the timing information into a high level language that can be compiled on the simulation host. The translator-profiler generated program is used to drive execution-driven simulations. The development of a translator-profiler for a hypothetical SISP is discussed at length. A technique for testing translator-profilers for errors by comparing simulation results to analytical predictions is also presented. The efficiency of hybrid simulation technique is also evaluated for simulations of QR decomposition and SVD algorithms implemented on arrays of SISP's.
Fault detection in full adder cellular arrays
(1970) Thakur, Sarvajit; Jump, J. Robert
This thesis illustrates the usefulness of the full adder as the elementary cell for designing cellular arrays for arithmetic. It Is shown that basic arithmetic operations, number system conversion, matrix operations and computation of common library functions can be implemented using full adder arrays. It is further shown that fault detection is particularly easy in full adder arrays. The four neighbor full adder array can be tested for the presence of a single faulty cell by applying exactly eight tests, irrespective of the size of the array. The full adder arrays for practical applications turn out to be a little more difficult for fault detection. The number of tests is shown to grow almost linearly with the number of primary input terminals in these arrays. In four neighbor half adder arrays the number of tests grows approximately as the square of the number of primary input terminals.
Fault detection in linear sequential circuits
(1969) Petrovic, Aleksa Sime; Jump, J. Robert
This thesis is concerned with the detection of non-transient faults in digital networks. A procedure for detection of faults in a simple controllable Linear Sequential Circuit (LSC) over GF(2) is developed. The following is assumed: 1) The faults are those which cause the LSC to behave as if some of its primary (external) or secondary (internal) terminals were permanently stuck at zero, or permanently stuck at one; 2) That all testing must be performed on the external terminals of the LSC. The characterizing matrix B, s vectors of the form AnBdv (v=l,2,...,s), s unit input vectors and the zero input vector are used instead of the fault table. (s is the number of primary input terminals, n is the dimension of LSC, A is its characteristic matrix and Sv is the unit input vector having 1 on the position v.) It is shown that the set of s+1 tests is sufficient to detect the existence of any fault that belongs to the set of defined faults. The test is defined here as a procedure consisting of: (a) Application of the unit input vector (or zero input vector) followed by 2n zero input vectors, (b) Comparison of the resulting output vectors with the vectors AnBdv. There are no faults in the LSC if and only if these vectors agree. It is further shown that for an arbitrary LSC over GF(2) realized in pseudo-canonical realization of m simple controllable LSCs, the set of (s+l).m tests is sufficient (m is the number of primary output terminals).
Incremental compilation and code generation
(1980) Bruce, Robert Ewing; Kennedy, Kenneth W.; Jump, J. Robert; Sinclair, James B.
Time sharing compilers are typically batch compilers that have been modified, via inclusion of a symbolic debugger, to "emulate" an interactive environment. The trend is away from interaction with the language processor and toward interaction with a common symbolic debugger. There are several problems with this approach: 1) It causes great time delays when a problem is isolated and a source change is necessary to correct a "bug". The use of an editor, compiler, and linkage editor is required to get back to the symbolic debugger. 2) Using a symbolic debugger requires knowledge of yet another language (the debugger's language). 3) Typically a symbolic debugger is written to work with more than one language and therefore has to house (sometimes incompatible) constructs for all of the languages it supports. The incremental compiler on the other hand has a rapid response to source changes. There is no need for a complete recompilation and linkage edit in order to re-execute the program after a change is made. The time required to make a change is proportional to the size of the change and not to the size of the program. The BASIC language processing system discussed in this work can operate as an incremental language processor as well as a Link-Ready (LR) code generating compiler. The term 'link-ready' denotes a type of relocatable object code that is suitable for linking with the BASIC library as well as with other user-written routines that have been separately compiled by BASIC or any other language processor. The compiler system operates in two modes, a link-ready code generating mode commonly called a batch compiler and an incremental or interactive mode that allows the user to enter source code lines in any order receiving error messages (if the source line is in error) as each line is entered. A BASIC program is first developed using the incremental compiler. Once the program is "debugged", it is compiled using the batch compiler to produce a more efficient executable module.

Browsing by Author "Jump, J. Robert"

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