Simple instruction set array processors are groups of regularly connected processors with small instruction sets and local memories. The processors are augmented by built-in communication instructions. Because of the complexity of implementing these systems, a method of simulating simple instruction set array processors is developed for evaluating the performance of architectures and algorithms. This technique, called hybrid instruction-level/execution-driven simulation, uses a translator-profiler to extract timing information from a program written in a simple instruction set processor's (SISP) assembly language. The translator-profiler converts the assembly language program and the timing information into a high level language that can be compiled on the simulation host. The translator-profiler generated program is used to drive execution-driven simulations. The development of a translator-profiler for a hypothetical SISP is discussed at length. A technique for testing translator-profilers for errors by comparing simulation results to analytical predictions is also presented. The efficiency of hybrid simulation technique is also evaluated for simulations of QR decomposition and SVD algorithms implemented on arrays of SISP's.