R-3 Repository :: Browsing by Author "Cavallaro, Joseph R."

Browsing by Author "Cavallaro, Joseph R."

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A Context-Aware Trust Framework for Resilient Distributed Cooperative Spectrum Sensing in Dynamic Settings
(IEEE, 2017) Vosoughi, Aida; Cavallaro, Joseph R.; Marshall, Alan
Cognitive radios enable dynamic spectrum access where secondary users (SUs) are allowed to operate on the licensed spectrum bands on an opportunistic noninterference basis. Cooperation among the SUs for spectrum sensing is essential for environments with deep shadows. In this paper, we study the adverse effect of insistent spectrum sensing data falsification (ISSDF) attack on iterative distributed cooperative spectrum sensing. We show that the existing trust management schemes are not adequate in mitigating ISSDF attacks in dynamic settings where the primary user (PU) of the band frequently transitions between active and inactive states. We propose a novel context-aware distributed trust framework for cooperative spectrum sensing in mobile cognitive radio ad hoc networks (CRAHN) that effectively alleviates different types of ISSDF attacks (Always-Yes, Always-No, and fabricating) in dynamic scenarios. In the proposed framework, the SU nodes evaluate the trustworthiness of one another based on the two possible contexts in which they make observations from each other: PU absent context and PU present context. We evaluate the proposed context-aware scheme and compare it against the existing context-oblivious trust schemes using theoretical analysis and extensive simulations of realistic scenarios of mobile CRAHNs operating in TV white space. We show that in the presence of a large set of attackers (as high as 60% of the network), the proposed context-aware trust scheme successfully mitigates the attacks and satisfy the false alarm and missed-detection rates of 10−2 and lower. Moreover, we show that the proposed scheme is scalable in terms of attack severity, SU network density, and the distance of the SU network to the PU transmitter.
A reconfigurable decoder architecture for wireless LAN and cellular systems
(2001) Chadha, Kanu; Cavallaro, Joseph R.
The rapid growth of wireless communications has led to the demand for communication devices which can support multiple standards and have the capability of switching from one to another on-the-fly. For instance, a device which could support the Wireless Local Area Network (LAN) and Wideband Code Division Multiple Access (WCDMA) standards would enable seamless communications in the indoor LAN network as well as the outdoor cellular environment. A key challenge involved in the building of such a communications device is the design of a flexible hardware architecture that can dynamically reconfigure itself to run different algorithms as required to support the different standards. In particular, the Viterbi decoding algorithm is used at the receiver of both WCDMA and WLAN systems to decode the convolutionally encoded data. The difference lies in the encoding parameters such as the constraint length, code rate and generator polynomials. In this thesis, we propose an architecture for a reconfigurable Viterbi decoder that can dynamically adapt to changes in the encoding parameters. The proposed architecture is implemented on a Field Programmable Gate Array (FPGA) device. The proposed architecture can be used to realize a Viterbi decoder which can support constraint lengths from 3 to 9 and rates 1/2 and 1/3.
A software simulation testbed for CDMA wireless communication systems
(1999) Sundaramurthy, Vishwas; Cavallaro, Joseph R.
This thesis develops a software wireless communication testbed which simulates a Code Division Multiple Access (CDMA) link. CDMA is a popular technology in cellular systems due to its superior capacity and performance. The designer of CDMA systems has a wide array of signal processing algorithms to choose from and a variety of operating environments to deal with. The testbed is a tool to evaluate these design options and trade-offs in different scenarios. The backbone of this system is a wireless CDMA multiuser link built using Simulink and Matlab. An efficient method of system modeling is used to speed up the simulations. This testbed can be used to study the performance of a CDMA wireless link with variation in system parameters and channel conditions. The use of Real-Time Workshop for DSP code generation is studied. This method is useful for rapid prototyping of algorithms and in DSP-based simulation acceleration of the testbed.
A systolic VLSI architecture for complex SVD
(1991) Hemkumar, Nariankadu Datatreya; Cavallaro, Joseph R.
This thesis presents a systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with "parallel ordering". As a basic step in the algorithm, a two-step, two-sided unitary transformation scheme is employed to diagonalize a complex 2 $\times$ 2 matrix. The transformations are tailored to the use of CORDIC (COordinate Rotation DIgital Computer) algorithms for high speed arithmetic. The complex SVD array is modeled on the Brent-Luk-VanLoan array for real SVD. An array with O($n\sp2$) processors is required to compute the SVD of a $n \times n$ matrix in O(n log n) time. An architecture for the complex 2 $\times$ 2 processor with an area complexity twice that of a real 2 $\times$ 2 processor, is shown to have the best area/time tradeoff for VLSI implementation. Despite the involved nature of computations on complex data, the computation time for the complex SVD array is less than three times that for a real SVD array with a similar CORDIC based implementation.
Accelerating Computer Vision Algorithms Using OpenCL Framework on Mobile Devices - A Case Study
(IEEE, 2013-06) Wang, Guohui; Xiong, Y.; Yun, Jay; Cavallaro, Joseph R.
Recently, general-purpose computing on graphics processing units (GPGPU) has been enabled on mobile devices thanks to the emerging heterogeneous programming models such as OpenCL. The capability of GPGPU on mobile devices opens a new era for mobile computing and can enable many computationally demanding computer vision algorithms on mobile devices. As a case study, this paper proposes to accelerate an exemplar-based inpainting algorithm for object removal on a mobile GPU using OpenCL. We discuss the methodology of exploring the parallelism in the algorithm as well as several optimization techniques. Experimental results demonstrate that our optimization strategies for mobile GPUs have significantly reduced the processing time and make computationally intensive computer vision algorithms feasible for a mobile device. To the best of the authors’ knowledge, this work is the first published implementation of general-purpose computing using OpenCL on mobile GPUs.
Adaptive Fault Detection and Tolerance for Robots
(TSI Press, 1994-08-01) Visinsky, Monica L.; Cavallaro, Joseph R.; Walker, Ian D.; Center for Multimedia Communication
In existing robot fault detection schemes, sensed values of the joint status (position, velocity, etc.) are typically compared against expected or desired values, and if a given threshold is exceeded, a fault is inferred. The thresholds tend to be empirically determined and held constant over a wide range of trajectories. This leads to false alarms when the threshold is too small to counter the error-inducing effects model inaccuracy and to undetected faults when the threshold is too large for the given situation. This paper presents new methods for adaptively choosing fault detection thresholds, subject to sensing and modeling inaccuracies and the changing status of the robot. Our approach chooses optimal thresholds based on a Singular Value Decomposition (SVD) of a specialized error regressor format of the dynamics to minimize the possibility of false alarms or undtected failures. The thresholds vary dynamically with the changing trajectory and configuration of the robot and with the robot's failure status. Examples of the fault detection scheme for a non-planar 3 DOF robot are given.
Advanced MIMO-CDMA receiver for interference suppression: Algorithms, system-on-chip architectures and design methodology
(2005) Guo, Yuanbin; Cavallaro, Joseph R.
MIMO (Multiple Input Multiple Output) technology is proposed in CDMA systems for much higher rate packet services. The receiver architecture is essential for the mobile devices to support high speed multimedia service. The design challenges come from both detection algorithms and hardware architectures. Much more complicated algorithms are required to suppress various interferences. However, the current hardware design architecture and methodology is falling far behind the requirements of small size, low cost and power consumption. System-On-Chip (SoC) architectures are a major revolution taking place in the design of integrated circuits due to many advantages in the power consumption and compact size. The VLSI-oriented complexity reduction of the numerical algorithms plays an essential role to design efficient real-time architectures. Thus, the thesis contributes to three major aspects: to propose high performance algorithms with realistic complexity in different channel conditions; to propose real-time SoC architectures with area/speed/power efficiency; and to propose an efficient design methodology for modelling, partitioning/binding, verification and synthesis of the wireless systems. Specifically, to cut the design cycle and enable extensive architecture tradeoff study, an integrated wireless development methodology by High-Level-Synthesis for joint algorithm and architecture optimization is proposed. To address the performance/complexity tradeoff, we propose two LMMSE equalizer algorithms and SoC architectures for different channel conditions. Both an FFT circulant MIMO equalizer and a frequency domain iterative equalizer are proposed to avoid Direct-Matrix-Inverse for the well-conditioned channel as well as long channels working in bad conditions respectively. We then propose a displacement Kalman equalizer with VLSI-oriented architectural optimization for better performance in fast fading environments. For systems with the multi-users' signaling, we propose an adaptive Parallel-Residue-Compensation architecture with stage and user specific weights by viewing the multiple transmitter antennas as virtual users to cancel the interferences explicitly. The increased accuracy in interference cancellation leads to significant performance gain over both the complete and partial PIC. The complexity is reduced by using the commonality to avoid the direct interference cancellation. Finally, dynamic power management schemes are proposed to reduce the power consumption in the VLSI architectures using the inherent features of the interference suppression algorithms.
Algorithms and architectures for channel estimation in wireless CDMA communication systems
(1999) Sengupta, Chaitali; Cavallaro, Joseph R.
Wireless cellular communication is witnessing a rapid growth in markets, technology, and range of services. An attractive approach for economical, spectrally efficient, and high quality digital cellular and personal communication services is the use of code division multiple access (CDMA) technology. The estimation of channel delays along with channel attenuation and phases of different users constitutes the first stage in the detection process at the receiving base station in a CDMA communication system. This stage, called channel parameter estimation, forms the bottleneck for the detection of users' bitstreams; both in terms of accuracy as well as execution time. In this thesis, we develop new algorithms and architectures to solve the CDMA channel estimation problem. We have first developed a framework that facilitates a computationally efficient solution to the combined problem of channel estimation and detection in a scenario involving multiple users, multiple paths, and multiple sensors at the receiver. The channel estimation approaches presented in this thesis, consist of two categories: (1) maximum likelihood based schemes, and (2) signal and noise subspace based schemes. The maximum likelihood approach is used to solve the complex multidimensional problem of channel estimation in the presence of multipath effects and concurrently using an antenna array at the base station receiver. Once the composite channel impulse response of each user is estimated, it is directly used in the detection process instead of first extracting the individual channel parameters, such as path delays and attenuation factors. This technique benefits from better performance as well as lower computational cost. Further, implementation issues of this algorithm, such as complexity reduction and fixed point error behaviour have also been addressed. Our contribution to the subspace-based solution includes extension of the basic algorithm to tracking of the channel parameters in a time varying environment. We have also applied algorithmic optimizations to reduce the computation required for the algorithm and developed architectural enhancements to improve the execution time, such as parallel processing and implementation on fixed point hardware.
An integrated CAD framework linking VLSI layout editors and process simulators
(1995) Sengupta, Chaitali; Cavallaro, Joseph R.
This thesis presents an Integrated CAD Framework which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. This will help designers to design more compact circuits, as they will be able to see the effect on manufactured silicon. The Framework identifies areas in a layout (in Magic or CIF format) that are more prone to problems arising out of the photolithographic process. It then creates the corresponding inputs for closer analysis with a process simulator (Depict) and analyzes the simulator outputs to decide whether the printed layout will match the designed mask for a particular set of process parameters. The designer can modify the original layout based upon this analysis. The Framework has been used to evaluate layouts for various process techniques. These evaluations illustrate the use of the Framework in determining the limits of any lithographic process.
Analysis of Robots for Hazardous Environments
(IEEE, 1997-01-01) Harpel, Barbara McLaughlin; Dugan, Joanne Bechta; Walker, Ian D.; Cavallaro, Joseph R.; Center for Multimedia Communication
Reliability analysis of fault tolerant systems often ignores the small probability that a failure might not be detected or, if detected, may not be properly handled. The probability that the failure is detected and properly handled is called coverage. Inclusion of coverage in reliability analysis is especially important when analyzing critical systems, systems which for some reason are not easily reparable, or systems whose failure can result in serious damage to the system or its surroundings. One example of a system which can cause such damage is a robot manipulator arm. Robots are being increasingly employed in remote and hazardous environments such as in space and in nuclear waste cleanup, and can exhibit a wild response to subsystem failure, damaging themselves and/or their surroundings. Addition of redundancy to such systems can increase their reliability by allowing continued operation in the presence of faults (provided that the fault is covered), an advantage in a system where repair is difficult or impossible. Coverage models have been used to analyze the behavior of fault-tolerant computer systems in the presence of faults, providing an estimate of the relative probability of an uncovered vs. a covered component failure (given that a fault has occurred) [1]. This paper extends the use of coverage models to the basic components of the joint of a robot and presents data utilizing the calculated coverage for a three-joint robot manipulator arm designed to operate in the plane.
Application-Specific Accelerators for Communications
(Springer Science+Business Media, LLC, 2010-01-01) Sun, Yang; Amiri, Kiarash; Brogioli, Michael; Cavallaro, Joseph R.; Center for Multimedia Communication
For computation-intensive digital signal processing algorithms, complexity is exceeding the processing capabilities of general-purpose digital signal processors (DSPs). In some of these applications, DSP hardware accelerators have been widely used to off-load a variety of algorithms from the main DSP host, including FFT, FIR/IIR filters, multiple-input multiple-output (MIMO) detectors, and error correction codes (Viterbi, Turbo, LDPC) decoders. Given power and cost considerations, simply implementing these computationally complex parallel algorithms with high-speed general-purpose DSP processor is not very efficient. However, not all DSP algorithms are appropriate for off-loading to a hardware accelerator. First, these algorithms should have data-parallel computations and repeated operations that are amenable to hardware implementation. Second, these algorithms should have a deterministic dataflow graph that maps to parallel datapaths. The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power. In this chapter, we focus on some of the basic and advanced digital signal processing algorithms for communications and cover major examples of DSP accelerators for communications.
Approximate Matrix Inversion for High-Throughput Data Detection in Large-Scale MIMO Uplink
(IEEE, 2013-05) Wu, M.; Yin, B.; Vosoughi, A.; Studer, C.; Cavallaro, Joseph R.; Dick, C.
The high processing complexity of data detection in the large-scale multiple-input multiple-output (MIMO) uplink necessitates high-throughput VLSI implementations. In this paper, we propose—to the best of our knowledge—first matrix inversion implementation suitable for data detection in systems having hundreds of antennas at the base station (BS). The underlying idea is to carry out an approximate matrix inversion using a small number of Neumann-series terms, which allows one to achieve near-optimal performance at low complexity. We propose a novel VLSI architecture to efficiently compute the approximate inverse using a systolic array and show reference FPGA implementation results for various system configurations. For a system where 128 BS antennas receive data from 8 single-antenna users, a single instance of our design processes 1.9Mmatrices/s on a Xilinx Virtex-7 FPGA, while using only 3.9% of the available slices and 3.6% of the available DSP48 units.
Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor
(1991) Kota, Kishore; Cavallaro, Joseph R.
This thesis describes the design of a systolic array for computing the Singular Value Decomposition (SVD) based on the Brent, Luk, Van Loan array. The use of COordinate Rotation DIgital Computer (CORDIC) arithmetic results in an efficient VLSI implementation of the processor that forms the basic unit of the array. A six-chip custom VLSI chip set for the processor was initially designed, fabricated in a 2.0$\mu$ CMOS n-well process, and tested. The CORDIC Array Process Element (CAPE), a single chip implementation, incorporates several enhancements based on a detailed error analysis of fixed-point CORDIC. The analysis indicates a need to normalize input values for inverse tangent computations. This scheme was implemented using a novel method that has $O(n\sp{1.5})$ hardware complexity. Use of previous techniques to implement such a normalization would require $O(n\sp2)$ hardware. Enhanced architectures, which reduce idle time in the array either through pipelining or by improving on a broadcast technique, are also presented.
Architecture and Algorithm for a Stochastic Soft-output MIMO Detector
(IEEE, 2007-11-04) Amiri, Kiarash; Radosavljevic, Predrag; Cavallaro, Joseph R.; CMC
In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, and several complexity reduction techniques are proposed to significantly reduce its cost from an architecture-implementation perspective. We also propose an efficient architecture to implement this detector. Finally, this detector is incorporated into an iterative detectiondecoding structure, and through simulations, it is shown that the overall frame error rate (FER) performance and complexity is of the same order as that of the conventional K-best sphere detector.
Architecture and Algorithm for a Stochastic Soft-output MIMO Detector
(IEEE, 2007-11-01) Amiri, Kiarash; Radosavljevic, Predrag; Cavallaro, Joseph R.; Center for Multimedia Communication
In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, and several complexity reduction techniques are proposed to significantly reduce its cost from an architecture-implementation perspective. We also propose an efficient architecture to implement this detector. Finally, this detector is incorporated into an iterative detection-decoding structure, and through simulations, it is shown that the overall frame error rate (FER) performance and complexity is of the same order as that of the conventional K-best sphere detector.
ARCHITECTURE DESIGN AND IMPLEMENTATION OF THE INCREASING RADIUS - LIST SPHERE DETECTOR ALGORITHM
(IEEE, 2009-04-01) Myllylä, Markus; Juntti, Markku; Cavallaro, Joseph R.; Center for Multimedia Communication
A list sphere detector (LSD) is an enhancement of a sphere detector (SD) that can be used to approximate the optimal MAP detector. In this paper, we introduce a novel architecture for the increasing radius (IR)-LSD algorithm, which is based on the Dijkstra’s algorithm. The parallelism possibilities are introduced in the presented architecture, which is also scalable for different multiple-input multiple-output (MIMO) systems. The novel architecture is implemented on a Virtex-IV field programmable gate array (FPGA) chip using high-level ANSI C++ language based Catapult C Synthesis tool from Mentor Graphics. The used word lengths, the latency of the design, and the required resources are presented and analyzed for 4 x 4 MIMO system with 16- quadrature amplitude modulation (QAM). The detector implementation achieves a maximum throughput of 12.1Mbps at high signal-to-noise ratio (SNR).
Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm
(IEEE, 2011-05-01) Myllylä, Markus; Cavallaro, Joseph R.; Juntti, Markku; Center for Multimedia Communication
Soft-output detection of a multiple-input–multiple-output (MIMO) signal pose a significant challenge in future wireless systems. In this paper, we introduce a soft-output modified metric first (MMF)-LSD algorithm for MIMO detection. We design a scalable architecture and address a method to decrease memory requirements. We provide implementation results for a spatial multiplexing (SM) system with four transmitted streams and with 16- and 64-quadrature amplitude modulation (QAM) on a 0.18- m CMOS application specific integrated circuit (ASIC) technology. The MFF-LSD implementation is more efficient than the depth first (DF) -LSD in the crucial low signal-to-noise rate (SNR)region and the detection rate of the 64-QAM implementation is 39.2 Mbps@26 db with 48.2 kGEs complexity.
Architecture for detection in MIMO wireless systems
(2007) Amiri, Kiarash; Cavallaro, Joseph R.
In this work, we study two main classes of detectors for spatially multiplexed Multiple-input Multiple-output (MIMO) systems. For the first group, i.e. hard-decision detectors, we study sphere detectors, and propose novel algorithms as well as efficient architectures which make them suitable for low-complexity implementations. Furthermore, different variations of such detectors are prototyped on Xilinx FPGAs embedded on Wireless Open-access Research Platform (WARP). The second class of detectors are soft-decision detectors where, generally, soft sphere detectors are used; however, we study a new class of detectors that can serve the same purpose through a stochastic approach known as Markov Chain Monte Carlo (MCMC) technique. A general architecture with various complexity reduction techniques is proposed for this scenario, and it is shown that MCMC achieves better performance compared to sphere detector; while it requires less computation when higher order modulations are used.
Architectures for a CORDIC SVD Processor
(SPIE - The International Society for Optical Engineering, 1986-08-21) Cavallaro, Joseph R.; Luk, Franklin T.
Architectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (CORDIC) algorithms to diagonalize 2X2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation.
Architectures for Cognitive Radio Testbeds and Demonstrators – An Overview
(IEEE, 2010-06-01) Gustafsson, Oscar; Amiri, Kiarash; Andersson, Dennis; Blad, Anton; Bonner, Christian; Cavallaro, Joseph R.; Declerck, Jeroen; Dejonghe, Antoine; Eliardsson, Patrik; Glasse, Miguel; Hayar, Aawatif; Hollevoet, Lieven; Hunter, Chris; Joshi, Madhura; Kaltenberger, Florian; Knopp, Raymond; Le, Khanh; Miljanic, Zoran; Murphy, Patrick; Naessens, Frederik; Nikaein, Navid; Nussbaum, Dominique; Pacalet, Renaud; Raghavan, Praveen; Sabharwal, Ashutosh; Sarode, Onkar; Spasojevic, Predrag; Sun, Yang; Tullberg, Hugo M.; Vander Aa, Tom; Van der Perre, Liesbet; Wetterwald, Michelle; Wu, Michael; Center for Multimedia Communication
Wireless communication standards are developed at an ever-increasing rate of pace, and significant amounts of effort is put into research for new communication methods and concepts. On the physical layer, such topics include MIMO, cooperative communication, and error control coding, whereas research on the medium access layer includes link control, network topology, and cognitive radio. At the same time, implementations are moving from traditional fixed hardware architectures towards software, allowing more efficient development. Today, field-programmable gate arrays (FPGAs) and regular desktop computers are fast enough to handle complete baseband processing chains, and there are several platforms, both open-source and commercial, providing such solutions. The aims of this paper is to give an overview of five of the available platforms and their characteristics, and compare the features and performance measures of the different systems.

Browsing by Author "Cavallaro, Joseph R."

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