Wireless cellular communication is witnessing a rapid growth in markets, technology, and range of services. An attractive approach for economical, spectrally efficient, and high quality digital cellular and personal communication services is the use of code division multiple access (CDMA) technology. The estimation of channel delays along with channel attenuation and phases of different users constitutes the first stage in the detection process at the receiving base station in a CDMA communication system. This stage, called channel parameter estimation, forms the bottleneck for the detection of users' bitstreams; both in terms of accuracy as well as execution time. In this thesis, we develop new algorithms and architectures to solve the CDMA channel estimation problem. We have first developed a framework that facilitates a computationally efficient solution to the combined problem of channel estimation and detection in a scenario involving multiple users, multiple paths, and multiple sensors at the receiver. The channel estimation approaches presented in this thesis, consist of two categories: (1) maximum likelihood based schemes, and (2) signal and noise subspace based schemes. The maximum likelihood approach is used to solve the complex multidimensional problem of channel estimation in the presence of multipath effects and concurrently using an antenna array at the base station receiver. Once the composite channel impulse response of each user is estimated, it is directly used in the detection process instead of first extracting the individual channel parameters, such as path delays and attenuation factors. This technique benefits from better performance as well as lower computational cost. Further, implementation issues of this algorithm, such as complexity reduction and fixed point error behaviour have also been addressed. Our contribution to the subspace-based solution includes extension of the basic algorithm to tracking of the channel parameters in a time varying environment. We have also applied algorithmic optimizations to reduce the computation required for the algorithm and developed architectural enhancements to improve the execution time, such as parallel processing and implementation on fixed point hardware.