VALID: Custom ASIC Verification and FPGA Education Platform

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameInternational Conference on Microelectronic Systems Education (MSE)en_US
dc.citation.firstpage66en_US
dc.citation.lastpage67en_US
dc.citation.locationAnaheim, CAen_US
dc.contributor.authorMurphy, Patricken_US
dc.contributor.authorWelsh, Eriken_US
dc.contributor.authorFrantz, Patricken_US
dc.contributor.authorHardy, Rickyen_US
dc.contributor.authorMohsenin, Tinooshen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:54:38Zen_US
dc.date.available2007-10-31T00:54:38Zen_US
dc.date.issued2003-06-01en_US
dc.date.modified2004-02-18en_US
dc.date.note2003-01-27en_US
dc.date.submitted2003-06-01en_US
dc.descriptionConference Paperen_US
dc.description.abstractThis paper describes VALID, a platform for testing student designed ASICs and for teaching the basics of FPGA design. VALID is designed to maximize ease of use from a student?s perspective while maintaining enough flexibility for its use as an FPGA development and instruction platform. This system was designed entirely by students, has been successfully manufactured and is currently being used in a number of courses at Rice.en_US
dc.identifier.citationP. Murphy, E. Welsh, P. Frantz, R. Hardy, T. Mohsenin and J. R. Cavallaro, "VALID: Custom ASIC Verification and FPGA Education Platform," 2003.en_US
dc.identifier.urihttps://hdl.handle.net/1911/20123en_US
dc.language.isoengen_US
dc.subjectasicen_US
dc.subjectfpgaen_US
dc.subjectvaliden_US
dc.subject.keywordasicen_US
dc.subject.keywordfpgaen_US
dc.subject.keywordvaliden_US
dc.titleVALID: Custom ASIC Verification and FPGA Education Platformen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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