Partitioned machine learning architecture
| dc.contributor.assignee | Rice University | en_US |
| dc.contributor.publisher | United States Patent and Trademark Office | en_US |
| dc.creator | Rouhani, Bita Darvish | en_US |
| dc.creator | Mirhoseini, Azalia | en_US |
| dc.creator | Koushanfar, Farinaz | en_US |
| dc.date.accessioned | 2024-04-04T17:22:03Z | en_US |
| dc.date.available | 2024-04-04T17:22:03Z | en_US |
| dc.date.filed | 2017-02-06 | en_US |
| dc.date.issued | 2024-03-05 | en_US |
| dc.description.abstract | A system may include a processor and a memory. The memory may include program code that provides operations when executed by the processor. The operations may include: partitioning, based at least on a resource constraint of a platform, a global machine learning model into a plurality of local machine learning models; transforming training data to at least conform to the resource constraint of the platform; and training the global machine learning model by at least processing, at the platform, the transformed training data with a first of the plurality of local machine learning models. | en_US |
| dc.digitization.specifications | This patent information was downloaded from the US Patent and Trademark website (http://www.uspto.gov/) as image-PDFs. The PDFs were OCRed for access purposes. | en_US |
| dc.format.extent | 27 | en_US |
| dc.identifier.patentID | US11922313B2 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/115480 | en_US |
| dc.language.iso | eng | en_US |
| dc.title | Partitioned machine learning architecture | en_US |
| dc.type | Utility patent | en_US |
| dc.type.dcmi | Text | en_US |
| dc.type.genre | patents | en_US |