Reliability-driven circuit optimization and design

dc.contributor.advisorMohanram, Kartiken_US
dc.creatorZhou, Qumingen_US
dc.date.accessioned2018-12-03T18:32:28Zen_US
dc.date.available2018-12-03T18:32:28Zen_US
dc.date.issued2007en_US
dc.description.abstractSingle-event upsets (SEUs) induced by high-energy neutrons and alpha particles have emerged as a key reliability threat to advanced commercial electronic components and systems. This dissertation describes gate-level radiation hardening techniques to improve the reliability of combinational circuits to SEUs. Such techniques have several advantages including low overhead, compatibility with the standard design flow, and enhancing classical fault avoidance and tolerance techniques. This dissertation begins by discussing the characteristics of SEUs in combinational circuits that can be used to improve circuit robustness. We develop numerical and compact circuit-level models to describe transient effects in circuits. Based on the models, we develop various solutions to successfully meet power-performance constraints for reliability-driven design optimization. The first solution is a rank-and-size approach where the most sensitive gates are sized to increase circuit robustness. To enable better design space exploration, we introduce an SEU constraint alongside traditional design constraints, such as area, power, and performance. This effort leads to new algorithms based on iterative and geometric programming optimizations. We also describe filter insertion in addition to sizing and dual-V DD to reduce the design overhead further. The effectiveness of these approaches is substantiated by experimental results. We describe the advantage and disadvantage of each approach to illustrate the applicability to various situations.en_US
dc.format.extent119 ppen_US
dc.identifier.callnoTHESIS E.E. 2008 ZHOUen_US
dc.identifier.citationZhou, Quming. "Reliability-driven circuit optimization and design." (2007) Diss., Rice University. <a href="https://hdl.handle.net/1911/103673">https://hdl.handle.net/1911/103673</a>.en_US
dc.identifier.digital304818259en_US
dc.identifier.urihttps://hdl.handle.net/1911/103673en_US
dc.language.isoengen_US
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.en_US
dc.subjectElectrical engineeringen_US
dc.subjectApplied sciencesen_US
dc.subjectCircuit designen_US
dc.subjectCircuit optimizationen_US
dc.subjectLow-poweren_US
dc.subjectReliabilityen_US
dc.subjectSingle-event upsetsen_US
dc.subjectSoft erroren_US
dc.titleReliability-driven circuit optimization and designen_US
dc.typeThesisen_US
dc.type.materialTexten_US
thesis.degree.departmentElectrical Engineeringen_US
thesis.degree.disciplineEngineeringen_US
thesis.degree.grantorRice Universityen_US
thesis.degree.levelDoctoralen_US
thesis.degree.nameDoctor of Philosophyen_US
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