Reliability-driven circuit optimization and design

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dc.contributor.advisorMohanram, Kartik
dc.creatorZhou, Quming
dc.date.accessioned2018-12-03T18:32:28Z
dc.date.available2018-12-03T18:32:28Z
dc.date.issued2007
dc.description.abstractSingle-event upsets (SEUs) induced by high-energy neutrons and alpha particles have emerged as a key reliability threat to advanced commercial electronic components and systems. This dissertation describes gate-level radiation hardening techniques to improve the reliability of combinational circuits to SEUs. Such techniques have several advantages including low overhead, compatibility with the standard design flow, and enhancing classical fault avoidance and tolerance techniques. This dissertation begins by discussing the characteristics of SEUs in combinational circuits that can be used to improve circuit robustness. We develop numerical and compact circuit-level models to describe transient effects in circuits. Based on the models, we develop various solutions to successfully meet power-performance constraints for reliability-driven design optimization. The first solution is a rank-and-size approach where the most sensitive gates are sized to increase circuit robustness. To enable better design space exploration, we introduce an SEU constraint alongside traditional design constraints, such as area, power, and performance. This effort leads to new algorithms based on iterative and geometric programming optimizations. We also describe filter insertion in addition to sizing and dual-V DD to reduce the design overhead further. The effectiveness of these approaches is substantiated by experimental results. We describe the advantage and disadvantage of each approach to illustrate the applicability to various situations.
dc.format.extent119 pp
dc.identifier.callnoTHESIS E.E. 2008 ZHOU
dc.identifier.citationZhou, Quming. "Reliability-driven circuit optimization and design." (2007) Diss., Rice University. <a href="https://hdl.handle.net/1911/103673">https://hdl.handle.net/1911/103673</a>.
dc.identifier.digital304818259
dc.identifier.urihttps://hdl.handle.net/1911/103673
dc.language.isoeng
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.
dc.subjectElectrical engineering
dc.subjectApplied sciences
dc.subjectCircuit design
dc.subjectCircuit optimization
dc.subjectLow-power
dc.subjectReliability
dc.subjectSingle-event upsets
dc.subjectSoft error
dc.titleReliability-driven circuit optimization and design
dc.typeThesis
dc.type.materialText
thesis.degree.departmentElectrical Engineering
thesis.degree.disciplineEngineering
thesis.degree.grantorRice University
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy
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