Single-event upsets (SEUs) induced by high-energy neutrons and alpha particles have emerged as a key reliability threat to advanced commercial electronic components and systems. This dissertation describes gate-level radiation hardening techniques to improve the reliability of combinational circuits to SEUs. Such techniques have several advantages including low overhead, compatibility with the standard design flow, and enhancing classical fault avoidance and tolerance techniques. This dissertation begins by discussing the characteristics of SEUs in combinational circuits that can be used to improve circuit robustness. We develop numerical and compact circuit-level models to describe transient effects in circuits. Based on the models, we develop various solutions to successfully meet power-performance constraints for reliability-driven design optimization. The first solution is a rank-and-size approach where the most sensitive gates are sized to increase circuit robustness. To enable better design space exploration, we introduce an SEU constraint alongside traditional design constraints, such as area, power, and performance. This effort leads to new algorithms based on iterative and geometric programming optimizations. We also describe filter insertion in addition to sizing and dual-V DD to reduce the design overhead further. The effectiveness of these approaches is substantiated by experimental results. We describe the advantage and disadvantage of each approach to illustrate the applicability to various situations.