Parallel VLSI Architectures for Real-Time Control of Redundant Robots

dc.citation.conferenceDate1991en_US
dc.citation.conferenceNameFourth ANS Topical Meeting on Robotics and Remote Systemsen_US
dc.citation.firstpage299en_US
dc.citation.lastpage309en_US
dc.citation.locationAlbuquerque, NMen_US
dc.contributor.authorWalker, Ian D.en_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-06-20T20:19:23Zen_US
dc.date.available2012-06-20T20:19:23Zen_US
dc.date.issued1991-02-01en_US
dc.description.abstractWe present new architectures for the efficient computation of redundant manipulator inverse kinematics. A key component of our architecture is the calculation in VLSI hardware of the Singular Value Decomposition of the manipulator Jacobian. By calculating the core of the problem in hardware, we can make full use of the redundancy by implementing more complex self-motion algorithms. Application-specific (subtask dependent) portions of the inverse kinematics are handled in parallel by an array of programmable Digital Signal Processing chips, which interface with the custom hardware and the host machine. Whole our application utilizes the range of Texas Instruments TMS series DSP chips applied to our 8 degree of freedom arm, the architecture and algorithm development is valid for general redundant manipulators and a wide range of processors currently available and under development commercially.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationI. D. Walker and J. R. Cavallaro, "Parallel VLSI Architectures for Real-Time Control of Redundant Robots," 1991.en_US
dc.identifier.urihttps://hdl.handle.net/1911/64282en_US
dc.language.isoengen_US
dc.publisherANSen_US
dc.titleParallel VLSI Architectures for Real-Time Control of Redundant Robotsen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
dc.type.dcmiTexten_US
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