High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | European Signal Processing Conference | en_US |
| dc.contributor.author | Radosavljevic, Predrag | en_US |
| dc.contributor.author | de Baynast, Alexandre | en_US |
| dc.contributor.author | Karkooti, Marjan | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:58:31Z | |
| dc.date.available | 2007-10-31T00:58:31Z | |
| dc.date.issued | 2006-09-01 | |
| dc.date.modified | 2006-06-02 | en_US |
| dc.date.note | 2006-06-02 | en_US |
| dc.date.submitted | 2006-09-01 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | A high throughput pipelined LDPC decoder that supports multiple code rates and codeword sizes is proposed. In order to increase memory throughput, irregular block structured parity-check matrices are designed with the constraint of equally distributed odd and even nonzero block-columns in each horizontal layer for the pre-determined set of code rates. The designed decoder achieves a data throughput of more than 1 Gb/s without sacrificing the error-correcting performance of capacity-approaching irregular block codes. The architecture is prototyped on an FPGA and synthesized for an ASIC design flow. | en_US |
| dc.identifier.citation | P. Radosavljevic, A. de Baynast, M. Karkooti and J. R. Cavallaro, "High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices," 2006. | |
| dc.identifier.uri | https://hdl.handle.net/1911/20211 | |
| dc.language.iso | eng | |
| dc.subject | LDPC codes | * |
| dc.subject | block-structured codes | * |
| dc.subject | layered belief propagation | * |
| dc.subject | flexible structured decoder design | * |
| dc.subject.keyword | LDPC codes | en_US |
| dc.subject.keyword | block-structured codes | en_US |
| dc.subject.keyword | layered belief propagation | en_US |
| dc.subject.keyword | flexible structured decoder design | en_US |
| dc.title | High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices | en_US |
| dc.type | Conference paper | |
| dc.type.dcmi | Text |