The design of a high performance interconnect for distributed shared memory multiprocessing
| dc.contributor.advisor | Bennett, John K. | en_US |
| dc.creator | Filippo, Michael Alan | en_US |
| dc.date.accessioned | 2009-06-04T08:11:29Z | en_US |
| dc.date.available | 2009-06-04T08:11:29Z | en_US |
| dc.date.issued | 1997 | en_US |
| dc.description.abstract | This thesis describes and evaluates the design of a high performance interconnect for use in a distributed shared memory multiprocessor. The network is based on the Peripheral Component Interconnect (PCI) bus and is fully compliant with PCI Specification Revision 2.1. It includes a high performance crossbar switch with support for up to sixteen fully-concurrent, packet-switched, duplex communication channels, each operating at 528 Mb/s. The design of the network was approached from three perspectives. First, we examined the architectural aspects of the network to determine its critical features. Second, we performed detailed simulations of three parallel applications, a useful approach for architectural validation and to provide precise approximations of subsystem requirements. Finally, we developed a complete logical and physical description of the datapaths and control logic used in the major subsystems, and created a state-accurate Verilog model to verify the physical design. All aspects of the resulting design were optimized to maximize network performance. Preliminary results indicate the network is capable of sustained throughput in excess of 3.5 Gb/s on real applications, sustained packet bandwidth exceeding 4.3 million 64-byte packets per second and packet latencies below 1$\mu$s. | en_US |
| dc.format.extent | 149 p. | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.callno | THESIS E.E. 1997 FILIPPO | en_US |
| dc.identifier.citation | Filippo, Michael Alan. "The design of a high performance interconnect for distributed shared memory multiprocessing." (1997) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/17084">https://hdl.handle.net/1911/17084</a>. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/17084 | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | en_US |
| dc.subject | Electronics | en_US |
| dc.subject | Electrical engineering | en_US |
| dc.subject | Computer science | en_US |
| dc.title | The design of a high performance interconnect for distributed shared memory multiprocessing | en_US |
| dc.type | Thesis | en_US |
| dc.type.material | Text | en_US |
| thesis.degree.department | Electrical Engineering | en_US |
| thesis.degree.discipline | Engineering | en_US |
| thesis.degree.grantor | Rice University | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science | en_US |
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