This thesis describes and evaluates the design of a high performance interconnect for use in a distributed shared memory multiprocessor. The network is based on the Peripheral Component Interconnect (PCI) bus and is fully compliant with PCI Specification Revision 2.1. It includes a high performance crossbar switch with support for up to sixteen fully-concurrent, packet-switched, duplex communication channels, each operating at 528 Mb/s. The design of the network was approached from three perspectives. First, we examined the architectural aspects of the network to determine its critical features. Second, we performed detailed simulations of three parallel applications, a useful approach for architectural validation and to provide precise approximations of subsystem requirements. Finally, we developed a complete logical and physical description of the datapaths and control logic used in the major subsystems, and created a state-accurate Verilog model to verify the physical design. All aspects of the resulting design were optimized to maximize network performance. Preliminary results indicate the network is capable of sustained throughput in excess of 3.5 Gb/s on real applications, sustained packet bandwidth exceeding 4.3 million 64-byte packets per second and packet latencies below 1μs.