Fault-Tolerant VLSI Processor Array for the SVD

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dc.citation.conferenceDate1989en_US
dc.citation.conferenceNameIEEE International Conference on Computer Design: VLSI in Computers & Processorsen_US
dc.citation.firstpage176
dc.citation.lastpage180
dc.citation.locationCambridge, MAen_US
dc.contributor.authorCavallaro, Joseph R.
dc.contributor.authorNear, Christopher D.
dc.contributor.authorUyar, M. Umit
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-05-18T19:30:49Z
dc.date.available2012-05-18T19:30:49Z
dc.date.issued1989-10-01eng
dc.description.abstractDynamic reconfiguration techniques are presented for a two-dimensional systolic array for the SVD of a matrix. Extra computation time is not required, since idle time inherent in the array is exploited. The scheme does not require additional spare processors and is easily implemented in VLSI. Only minor hardware and communication time increases within each processing element are required.en_US
dc.description.sponsorshipAT&T Bell Laboratoriesen_US
dc.identifier.citationJ. R. Cavallaro, C. D. Near and M. U. Uyar, "Fault-Tolerant VLSI Processor Array for the SVD," 1989.*
dc.identifier.doihttp://dx.doi.org/10.1109/ICCD.1989.63351en_US
dc.identifier.urihttps://hdl.handle.net/1911/64164
dc.language.isoengen
dc.publisherIEEE Computer Society Pressen_US
dc.titleFault-Tolerant VLSI Processor Array for the SVDen_US
dc.typeConference paperen_US
dc.type.dcmiTexten
dc.type.dcmiTexten_US
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