High-Level Design Tools for Complex DSP Applications

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dc.citation.firstpage133en_US
dc.citation.lastpage155en_US
dc.citation.volumeNumberChapter 8en_US
dc.contributor.authorSun, Yangen_US
dc.contributor.authorAmiri, Kiarashen_US
dc.contributor.authorWang, Guohuien_US
dc.contributor.authorYin, Beien_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorLy, Taien_US
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-07-26T15:33:44Zen_US
dc.date.available2012-07-26T15:33:44Zen_US
dc.date.issued2012-07-12en_US
dc.description.abstractHigh-level synthesis design methodology - High level synthesis (HLS) [1], also known as behavioral synthesis and algorithmic synthesis, is a design process in which a high level, functional description of a design is automatically compiled into a RTL implementation that meets certain user specified design constraints. The HLS design description is ‘high level’ compared to RTL in two aspects: design abstraction, and specification language.en_US
dc.identifier.citationY. Sun, K. Amiri, G. Wang, B. Yin, J. R. Cavallaro and T. Ly, "High-Level Design Tools for Complex DSP Applications," vol. Chapter 8, 2012.en_US
dc.identifier.otherhttp://store.elsevier.com/product.jsp?isbn=9780123865359&_requestid=111075en_US
dc.identifier.urihttps://hdl.handle.net/1911/64508en_US
dc.language.isoengen_US
dc.publisherElsevier, Waltham, MAen_US
dc.titleHigh-Level Design Tools for Complex DSP Applicationsen_US
dc.typeBook chapteren_US
dc.type.dcmiTexten_US
dc.type.dcmiTexten_US
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