Porous SiOx materials for improvement in SiOx switching device performances
dc.contributor.assignee | Rice University | |
dc.contributor.publisher | United States Patent and Trademark Office | |
dc.creator | Tour, James M. | |
dc.creator | Wang, Gunuk | |
dc.creator | Yang, Yang | |
dc.creator | Ji, Yongsung | |
dc.date.accessioned | 2018-08-23T18:27:56Z | |
dc.date.available | 2018-08-23T18:27:56Z | |
dc.date.filed | 2014-11-19 | |
dc.date.issued | 2018-06-12 | |
dc.description.abstract | A porous memory device, such as a memory or a switch, may provide a top and bottom electrodes with a memory material layer (e.g. SiOx) positioned between the electrodes. The memory material layer may provide a nanoporous structure. In some embodiments, the nanoporous structure may be formed electrochemically, such as from anodic etching. Electroformation of a filament through the memory material layer may occur internally through the layer rather than at an edge at extremely low electro-forming voltages. The porous memory device may also provide multi-bit storage, high on-off ratios, long high-temperature lifetime, excellent cycling endurance, fast switching, and lower power consumption. | |
dc.digitization.specifications | This patent information was downloaded from the US Patent and Trademark website (http://www.uspto.gov/) as image-PDFs. The PDFs were OCRed for access purposes | |
dc.format.extent | 27 | |
dc.identifier.citation | Tour, James M., Wang, Gunuk, Yang, Yang and Ji, Yongsung, "Porous SiOx materials for improvement in SiOx switching device performances." Patent US9997705B2. issued 2018-06-12. Retrieved from <a href="https://hdl.handle.net/1911/102490">https://hdl.handle.net/1911/102490</a>. | |
dc.identifier.patentID | US9997705B2 | |
dc.identifier.uri | https://hdl.handle.net/1911/102490 | |
dc.language.iso | eng | |
dc.title | Porous SiOx materials for improvement in SiOx switching device performances | |
dc.type | Utility patent | |
dc.type.dcmi | Text | |
dc.type.genre | patents |
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