CORDIC Arithmetic for an SVD Processor

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dc.citation.bibtexNamearticleen_US
dc.citation.firstpage271
dc.citation.issueNumber3en_US
dc.citation.journalTitleJournal of Parallel and Distributed Computingen_US
dc.citation.lastpage290
dc.citation.volumeNumber5en_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorLuk, Franklin T.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:38:18Z
dc.date.available2007-10-31T00:38:18Z
dc.date.issued1988-06-20
dc.date.modified2003-11-04en_US
dc.date.submitted2001-08-31en_US
dc.descriptionJournal Paperen_US
dc.description.abstractArithmetic issues in the calculation of the Singular Value Decomposition (SVD) are discussed. Traditional algorithms using hardware division and square root are replaced with the special purpose CORDIC algorithms for computing vector rotations and inverse tangents. The CORDIC 2 x 2 SVD processor can be twice as fast as one assembled from traditional hardware units. A prototype VLSI implementation of a CORDIC SVD processor array is planned for use in real-time signal processing applications.en_US
dc.identifier.citationJ. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor," <i>Journal of Parallel and Distributed Computing,</i> vol. 5, no. 3, 1988.
dc.identifier.doihttp://dx.doi.org/10.1109/ARITH.1987.6158686en_US
dc.identifier.urihttps://hdl.handle.net/1911/19758
dc.language.isoeng
dc.subjectSingular Value Decomposition (SVD)*
dc.subjectCORDIC algorithms*
dc.subjectVLSI*
dc.subject.keywordSingular Value Decomposition (SVD)en_US
dc.subject.keywordCORDIC algorithmsen_US
dc.subject.keywordVLSIen_US
dc.titleCORDIC Arithmetic for an SVD Processoren_US
dc.typeJournal article
dc.type.dcmiText
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