Hardware/Software Co-design Methodology and DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.5G Mobile Receivers
| dc.citation.conferenceDate | 2006 | en_US |
| dc.citation.conferenceName | IEEE International Midwest Symposium on Circuits and Systems | en_US |
| dc.citation.location | San Juan, PR | en_US |
| dc.contributor.author | Brogioli, Michael | |
| dc.contributor.author | Radosavljevic, Predrag | |
| dc.contributor.author | Cavallaro, Joseph R. | |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-14T16:38:51Z | |
| dc.date.available | 2012-06-14T16:38:51Z | |
| dc.date.issued | 2006-08-01 | eng |
| dc.description.abstract | This paper presents a DSP/FPGA hardware/software partitioning methodology for signal processing workloads. The example workload is the channel equalization and user-detection in HSDPA wireless standard for 3.5G mobile handsets. Channel equalization and user-detection is a major component of receiver baseband processing and requires strict adherence to real time deadlines. By intelligently exploring the embedded design space, this paper presents a hardware/software system-on-chip partitionings that utilizes both DSP and FPGA based coprocessors to meet and exceed the real time data rates determined by the HSDPA standard. Hardware and software partitioning strategies are discussed with respect to real time processing deadlines, while an SOC simulation toolset is presented as vehicle for prototyping embedded architectures. | en_US |
| dc.description.sponsorship | Nokia Inc. | en_US |
| dc.description.sponsorship | Texas Instruments | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | M. Brogioli, P. Radosavljevic and J. R. Cavallaro, "Hardware/Software Co-design Methodology and DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.5G Mobile Receivers," 2006. | |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=6704085062299749324&hl=en&as_sdt=0,44 | |
| dc.identifier.uri | https://hdl.handle.net/1911/64269 | |
| dc.language.iso | eng | en |
| dc.publisher | IEEE | en_US |
| dc.subject | DSP/FPGA | en_US |
| dc.subject | System-on-Chip | en_US |
| dc.subject | Partitioning | en_US |
| dc.subject | Embedded design space | en_US |
| dc.title | Hardware/Software Co-design Methodology and DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.5G Mobile Receivers | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en |
| dc.type.dcmi | Text | en_US |