Memory-Hierarchy Management
| dc.contributor.author | Carr, Steve | en_US |
| dc.date.accessioned | 2017-08-02T22:03:18Z | en_US |
| dc.date.available | 2017-08-02T22:03:18Z | en_US |
| dc.date.issued | 1992-09 | en_US |
| dc.date.note | September 1992 | en_US |
| dc.description | This work was also published as a Rice University thesis/dissertation: http://hdl.handle.net/1911/16605 | en_US |
| dc.description.abstract | The trend in high-performance microprocessor design is toward increasing computational power on the chip. Microprocessors can now process dramatically more data per machine cycle than previous models. Unfortunately, memory speeds have not kept pace.The result is an imbalance between computation speed and memory speed. This imbalance is leading machine designers to use more complicated memory hierarchies. In turn, programmers are explicitly restructuring codes to perform well on particular memory systems, leading to machine-specific programs. It is our belief that machine-specific programming is a step in the wrong direction. Compilers, not programmers, should handle machine-specific implementation details. To this end, this thesis develops and experiments with compiler algorithms that manage the memory hierarchy of a machine for floating-point intensive numerical codes. Specifically, we address the following issues: Scalar replacement. Lack of information concerning the flow of array values in standard data-flow analysis prevents the capturing of array reuse in registers. We develop and experiment with a technique to perform scalar replacement in the presence of conditional-control flow to expose array reuse to standard data-flow algorithms. Unroll-and-jam. Many loops require more data per cycle than can be processed by the target machine. We present and experiment with an automatic technique to apply unroll-and-jam to such loops to reduce their memory requirements. Loop Interchange. Cache locality in programs run on advanced microprocessors is critical to performance. We develop and experiment with a technique to order loops within a nest to attain good cache locality. Blocking. Iteration-space blocking is a technique used to attain temporal locality within cache. Although it has been applied to "simple" kernels, there has been no investigation into its applicability over a range of algorithmic styles. We show how to apply blocking to loops with trapezoidal-, rhomboidal-, and triangular-shaped iteration spaces. In addition, we show how to overcome certain complex dependence patterns. Experiments with the above techniques have shown that integer-factor speedups on a single chip are possible. These results reveal that many numerical algorithms can be expressed in a natural, machine-independent form while retaining good memory performance through the use of compiler optimizations. | en_US |
| dc.format.extent | 106 pp | en_US |
| dc.identifier.citation | Carr, Steve. "Memory-Hierarchy Management." (1992) https://hdl.handle.net/1911/96430. | en_US |
| dc.identifier.digital | TR92-310 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/96430 | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | You are granted permission for the noncommercial reproduction, distribution, display, and performance of this technical report in any format, but this permission is only for a period of forty-five (45) days from the most recent time that you verified that this technical report is still available from the Computer Science Department of Rice University under terms that include this permission. All other rights are reserved by the author(s). | en_US |
| dc.title | Memory-Hierarchy Management | en_US |
| dc.type | Technical report | en_US |
| dc.type.dcmi | Text | en_US |
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