Improving Memory Hierarchy Performance for Irregular Applications

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dc.contributor.authorKennedy, Ken
dc.contributor.authorMellor-Crummey, John
dc.contributor.authorWhalley, David
dc.date.accessioned2017-08-02T22:03:46Z
dc.date.available2017-08-02T22:03:46Z
dc.date.issued1999-03-10
dc.date.noteMarch 10, 1999
dc.description.abstractThe gap between CPU speed and memory speed in modern computer systems is widening as new generations of hardware are introduced. Loop blocking and prefetching transformations help bridge this gap for regular applications; however, these techniques don't deal well with irregular applications. This paper investigates using data and computation reordering strategies to improve memory hierarchy utilization for irregular applications on systems with multi-level memory hierarchies. We introduce multi-level blocking as a new computation reordering strategy and present novel integrations of computation and data reordering using space-filling curves. In experiments that applied a combination of data and computation reorderings to two irregular programs, overall execution time dropped by about a factor of two.
dc.format.extent13 pp
dc.identifier.citationKennedy, Ken, Mellor-Crummey, John and Whalley, David. "Improving Memory Hierarchy Performance for Irregular Applications." (1999) https://hdl.handle.net/1911/96505.
dc.identifier.digitalTR99-336
dc.identifier.urihttps://hdl.handle.net/1911/96505
dc.language.isoeng
dc.rightsYou are granted permission for the noncommercial reproduction, distribution, display, and performance of this technical report in any format, but this permission is only for a period of forty-five (45) days from the most recent time that you verified that this technical report is still available from the Computer Science Department of Rice University under terms that include this permission. All other rights are reserved by the author(s).
dc.titleImproving Memory Hierarchy Performance for Irregular Applications
dc.typeTechnical report
dc.type.dcmiText
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