Semi-Parallel Architectures For Real-time LDPC Coding
| dc.citation.bibtexName | mastersthesis | en_US |
| dc.citation.journalTitle | Masters Thesis | en_US |
| dc.citation.location | Houston, TX | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.creator | Karkooti, Marjan | en_US |
| dc.date.accessioned | 2007-10-31T00:49:02Z | en_US |
| dc.date.available | 2007-10-31T00:49:02Z | en_US |
| dc.date.issued | 2004-05-01 | en_US |
| dc.date.modified | 2004-08-30 | en_US |
| dc.date.submitted | 2004-05-06 | en_US |
| dc.description | Masters Thesis | en_US |
| dc.description.abstract | Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. ow Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area-time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3,6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes. | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | Nokia/Texas Instruments | en_US |
| dc.description.sponsorship | National Instruments | en_US |
| dc.identifier.citation | "Semi-Parallel Architectures For Real-time LDPC Coding," <i>Masters Thesis,</i> 2004. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/20000 | en_US |
| dc.language.iso | eng | en_US |
| dc.subject | Reconfigurable architecture | en_US |
| dc.subject | FPGA implementation | en_US |
| dc.subject | channel coding | en_US |
| dc.subject | parallel architecture | en_US |
| dc.subject | area-time tradeoffs. | en_US |
| dc.subject.keyword | Reconfigurable architecture | en_US |
| dc.subject.keyword | FPGA implementation | en_US |
| dc.subject.keyword | channel coding | en_US |
| dc.subject.keyword | parallel architecture | en_US |
| dc.subject.keyword | area-time tradeoffs. | en_US |
| dc.title | Semi-Parallel Architectures For Real-time LDPC Coding | en_US |
| dc.type | Thesis | en_US |
| dc.type.dcmi | Text | en_US |
| thesis.degree.level | Masters | en_US |
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