Efficient simulation and utilization of a parallel digital signal processing architecture

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dc.contributor.advisorJump, J. Robert
dc.contributor.advisorSinclair, James B.
dc.creatorFoundoulis, William James
dc.date.accessioned2009-06-04T00:39:38Z
dc.date.available2009-06-04T00:39:38Z
dc.date.issued1989
dc.description.abstractIn this study we discuss the development and validation of an efficient and accurate execution-driven simulation of the Texas Instruments Odyssey System, a parallel configuration of digital signal processors. We also evaluate the performance of a high-level parallel programming interface, Odyssey Concurrent C, designed to effectively utilize the parallelism available in the Odyssey architecture. Parallel versions of three dissimilar algorithms--merge sort, 2-dimensional convolution, and successive over-relaxation--have been run on both the Odyssey and the simulator. Quantitative differences between performance results obtained on the Odyssey and those predicted by simulation are enumerated, and shown to validate the accuracy of the execution-driven approach. The simulation is also shown to be efficient relative to the degree of accuracy obtainable. Finally, the Odyssey Concurrent C utilities are shown to provide a flexible and effective mechanism for managing parallelism in the Odyssey environment.
dc.format.extent72 p.en_US
dc.format.mimetypeapplication/pdf
dc.identifier.callnoTHESIS E.E. 1989 FOUNDOULIS
dc.identifier.citationFoundoulis, William James. "Efficient simulation and utilization of a parallel digital signal processing architecture." (1989) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/13357">https://hdl.handle.net/1911/13357</a>.
dc.identifier.urihttps://hdl.handle.net/1911/13357
dc.language.isoeng
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.
dc.subjectElectronics
dc.subjectElectrical engineering
dc.subjectComputer science
dc.titleEfficient simulation and utilization of a parallel digital signal processing architecture
dc.typeThesis
dc.type.materialText
thesis.degree.departmentElectrical Engineering
thesis.degree.disciplineEngineering
thesis.degree.grantorRice University
thesis.degree.levelMasters
thesis.degree.nameMaster of Science
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