Hardware Transactional Persistent Memory

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dc.contributor.advisorVarman, Peter
dc.creatorGiles, Ellis Robinson
dc.date.accessioned2019-05-16T18:54:17Z
dc.date.available2019-05-16T18:54:17Z
dc.date.created2019-05
dc.date.issued2019-01-31
dc.date.submittedMay 2019
dc.date.updated2019-05-16T18:54:17Z
dc.description.abstractRecent years have witnessed a sharp shift towards real-time data-driven and high-throughput applications, impelled by pervasive multi-core architectures and parallel programming models. This shift has spurred a broad adoption of in-memory databases and massively-parallel transaction processing across scientific, business, and industrial application domains. However, these applications are severely handicapped by the difficulties in maintaining persistence on typical durable media like hard-disk drives (HDDs) and solid-state drives (SSDs) without sacrificing either performance or reliability. The ending of Moore's Law and Dennard Scaling have further slowed performance gains and scalability of these applications. Two emerging hardware developments hold enormous promise for transformative gains in both speed and scalability of concurrent data-intensive applications. The first is the arrival of Persistent Memory, or PM, a generic term for byte-addressable non-volatile memories, such as Intel's 3D XPoint technology. The second is the availability of CPU-based transaction support known as Hardware Transactional Memory, or HTM, which makes it easier for applications to exploit multi-core concurrency without the need for expensive lock-based software. This thesis introduces Hardware Transactional Persistent Memory, the first union of HTM with PM without any changes to known processor designs or protocols, allowing for high-performance, concurrent, and durable transactions. The techniques presented are supported on three pillars: handling uncontrolled cache evictions from the processor cache hierarchy, logging to resist failure during persistent memory updates, and transaction ordering to permit consistent recovery from a machine crash. We develop pure software solutions that work with existing processor architectures as well as software-assisted solutions that exploit external memory controller hardware support. The thesis also introduces the notion of relaxed versus strict durability, allowing individual applications to tradeoff performance against robustness, while guaranteeing recovery to a consistent system state.
dc.format.mimetypeapplication/pdf
dc.identifier.citationGiles, Ellis Robinson. "Hardware Transactional Persistent Memory." (2019) Diss., Rice University. <a href="https://hdl.handle.net/1911/105386">https://hdl.handle.net/1911/105386</a>.
dc.identifier.urihttps://hdl.handle.net/1911/105386
dc.language.isoeng
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.
dc.subjectPersistent Memory
dc.subjectPM
dc.subjectHardware Transactional Memory
dc.subjectHTM
dc.subjectStorage Class Memory
dc.subjectSCM
dc.subjectNVM
dc.subjectComputer Engineering
dc.subjectTransactions
dc.subjectHPC
dc.subjectHigh Performance Computing
dc.subjectOptane
dc.subjectRTM
dc.titleHardware Transactional Persistent Memory
dc.typeThesis
dc.type.materialText
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineEngineering
thesis.degree.grantorRice University
thesis.degree.levelDoctoral
thesis.degree.majorComputer Engineering
thesis.degree.nameDoctor of Philosophy
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