Recent years have witnessed a sharp shift towards real-time data-driven and high-throughput applications, impelled by pervasive multi-core architectures and parallel programming models. This shift has spurred a broad adoption of in-memory databases and massively-parallel transaction processing across scientific, business, and industrial application domains. However, these applications are severely handicapped by the difficulties in maintaining persistence on typical durable media like hard-disk drives (HDDs) and solid-state drives (SSDs) without sacrificing either performance or reliability. The ending of Moore's Law and Dennard Scaling have further slowed performance gains and scalability of these applications.

Two emerging hardware developments hold enormous promise for transformative gains in both speed and scalability of concurrent data-intensive applications. The first is the arrival of Persistent Memory, or PM, a generic term for byte-addressable non-volatile memories, such as Intel's 3D XPoint technology. The second is the availability of CPU-based transaction support known as Hardware Transactional Memory, or HTM, which makes it easier for applications to exploit multi-core concurrency without the need for expensive lock-based software.

This thesis introduces Hardware Transactional Persistent Memory, the first union of HTM with PM without any changes to known processor designs or protocols, allowing for high-performance, concurrent, and durable transactions. The techniques presented are supported on three pillars: handling uncontrolled cache evictions from the processor cache hierarchy, logging to resist failure during persistent memory updates, and transaction ordering to permit consistent recovery from a machine crash. We develop pure software solutions that work with existing processor architectures as well as software-assisted solutions that exploit external memory controller hardware support. The thesis also introduces the notion of relaxed versus strict durability, allowing individual applications to tradeoff performance against robustness, while guaranteeing recovery to a consistent system state.