Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems

dc.citation.conferenceDate2006en_US
dc.citation.conferenceNameIEEE Real-Time and Embedded Technology and Applications Symposium; Work in Progress Sessionen_US
dc.citation.firstpage29en_US
dc.citation.lastpage32en_US
dc.contributor.authorBrogioli, Michael C.en_US
dc.contributor.authorGadhiok, Maniken_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-06-14T19:38:31Zen_US
dc.date.available2012-06-14T19:38:31Zen_US
dc.date.issued2006-04-01en_US
dc.description.abstractThis paper shows how iterative hardware/software partitioning in heterogeneous DSP/FPGA based embedded systems can be utilized to achieve real-time deadlines of modern 3GPP wireless equalization workloads. By utilizing a well defined set of application partitioning criteria in tandem with SOC simulation tools, we are able to show a greater than six fold improvement in application performance and ultimately meet, and even exceed real-time data processing deadlines.en_US
dc.identifier.citationM. C. Brogioli, M. Gadhiok and J. R. Cavallaro, "Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems," 2006.en_US
dc.identifier.otherhttp://scholar.google.com/scholar?cluster=11702462114251271950&hl=en&as_sdt=0,44en_US
dc.identifier.urihttps://hdl.handle.net/1911/64274en_US
dc.language.isoengen_US
dc.publisherIEEEen_US
dc.subjectReal time systemsen_US
dc.subjectEmbedded systemsen_US
dc.subjectFPGAen_US
dc.subjectSystem partitioningen_US
dc.subjectWireless applicationsen_US
dc.titleDesign and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systemsen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
dc.type.dcmiTexten_US
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