Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems
dc.citation.conferenceDate | 2006 | en_US |
dc.citation.conferenceName | IEEE Real-Time and Embedded Technology and Applications Symposium; Work in Progress Session | en_US |
dc.citation.firstpage | 29 | en_US |
dc.citation.lastpage | 32 | en_US |
dc.contributor.author | Brogioli, Michael C. | en_US |
dc.contributor.author | Gadhiok, Manik | en_US |
dc.contributor.author | Cavallaro, Joseph R. | en_US |
dc.contributor.org | Center for Multimedia Communication | en_US |
dc.date.accessioned | 2012-06-14T19:38:31Z | en_US |
dc.date.available | 2012-06-14T19:38:31Z | en_US |
dc.date.issued | 2006-04-01 | en_US |
dc.description.abstract | This paper shows how iterative hardware/software partitioning in heterogeneous DSP/FPGA based embedded systems can be utilized to achieve real-time deadlines of modern 3GPP wireless equalization workloads. By utilizing a well defined set of application partitioning criteria in tandem with SOC simulation tools, we are able to show a greater than six fold improvement in application performance and ultimately meet, and even exceed real-time data processing deadlines. | en_US |
dc.identifier.citation | M. C. Brogioli, M. Gadhiok and J. R. Cavallaro, "Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems," 2006. | en_US |
dc.identifier.other | http://scholar.google.com/scholar?cluster=11702462114251271950&hl=en&as_sdt=0,44 | en_US |
dc.identifier.uri | https://hdl.handle.net/1911/64274 | en_US |
dc.language.iso | eng | en_US |
dc.publisher | IEEE | en_US |
dc.subject | Real time systems | en_US |
dc.subject | Embedded systems | en_US |
dc.subject | FPGA | en_US |
dc.subject | System partitioning | en_US |
dc.subject | Wireless applications | en_US |
dc.title | Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems | en_US |
dc.type | Conference paper | en_US |
dc.type.dcmi | Text | en_US |
dc.type.dcmi | Text | en_US |