An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
dc.citation.bibtexName | article | en_US |
dc.citation.journalTitle | EURASIP Journal on Applied Signal Processing | en_US |
dc.contributor.author | Guo, Yuanbin | en_US |
dc.contributor.author | Zhang, Jianzhong (Charlie) | en_US |
dc.contributor.author | McCain, Dennis | en_US |
dc.contributor.author | Cavallaro, Joseph R. | en_US |
dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
dc.date.accessioned | 2007-10-31T00:45:57Z | en_US |
dc.date.available | 2007-10-31T00:45:57Z | en_US |
dc.date.issued | 2005-12-01 | en_US |
dc.date.modified | 2005-06-25 | en_US |
dc.date.submitted | 2005-06-24 | en_US |
dc.description | Journal Paper | en_US |
dc.description.abstract | In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF x NF) with O((NF)³) complexity to some FFT operations with O(NF log<sub>2</sub>(F)) complexity and the inverse of some (N x N) sub-matrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the (4 x 4) high-order receiver from partitioned (2 x 2) sub-matrices. This leads to more parallel VLSI design with 3x further complexity reduction. Comparative study with both the Conjugate-Gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C High-Level-Synthesis methodology. | en_US |
dc.identifier.citation | Y. Guo, J. (. Zhang, D. McCain and J. R. Cavallaro, "An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture," <i>EURASIP Journal on Applied Signal Processing,</i> 2005. | en_US |
dc.identifier.doi | http://dx.doi.org/10.1155/ASP/2006/57134 | en_US |
dc.identifier.uri | https://hdl.handle.net/1911/19929 | en_US |
dc.language.iso | eng | en_US |
dc.subject | MIMO equalizer | en_US |
dc.subject | circulant | en_US |
dc.subject | VLSI | en_US |
dc.subject.keyword | MIMO equalizer | en_US |
dc.subject.keyword | circulant | en_US |
dc.subject.keyword | VLSI | en_US |
dc.title | An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture | en_US |
dc.type | Journal article | en_US |
dc.type.dcmi | Text | en_US |
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