In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF x NF) with O((NF)³) complexity to some FFT operations with O(NF log₂(F)) complexity and the inverse of some (N x N) sub-matrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the (4 x 4) high-order receiver from partitioned (2 x 2) sub-matrices. This leads to more parallel VLSI design with 3x further complexity reduction. Comparative study with both the Conjugate-Gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C High-Level-Synthesis methodology.