This thesis presents an Integrated CAD Framework which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. This will help designers to design more compact circuits, as they will be able to see the effect on manufactured silicon. The Framework identifies areas in a layout (in Magic or CIF format) that are more prone to problemsmask for a particular set of process parameters. The designer can modify the original layout based arising out of the photolithographic process. It then creates the corresponding in-puts for closer analysis with a process simulator (Depict) and analyzes the simulator outputs to decide whether the printed layout will match the designed upon this analysis. The Framework has been used to evaluate layouts for various process techniques. These evaluations illustrate the use of the Framework in determining the limits of any lithographic process.