An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators

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dc.citation.conferenceDate1996en_US
dc.citation.conferenceNameSPIE Conference on Optical Microlithography IXen_US
dc.citation.firstpage244
dc.citation.lastpage252
dc.citation.locationSanta Clara, CAen_US
dc.contributor.authorSengupta, Chaitali
dc.contributor.authorErdelyi, Miklos
dc.contributor.authorBor, Zsolt
dc.contributor.authorCavallaro, Joseph R.
dc.contributor.authorSmayling, Michael C.
dc.contributor.authorSzabo, Gabor
dc.contributor.authorTittel, Frank K.
dc.contributor.authorWilson, William L.
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-06-15T21:52:21Z
dc.date.available2012-06-15T21:52:21Z
dc.date.issued1996-03-01eng
dc.description.abstractAs feature sizes in VLSI circuits extend into the far sub-micron range, new process techniques, such as using phase shifting masks for photolithography, will be needed. Under these conditions, the only means for the circuit designer to design compact and efficient circuits with good yield capabilities is to be able to see t he effect of different design approaches on manufactured silicon, instead of solely relying on conservative general design rules. The Integrated CAD Framework accomplishes this by providing a link between a layout editor (Magic), advanced photolithographic techniques such as phase shifted masks, and a process simulator (Depict). This paper discusses some applications of this tool. A non-conventional process technique involving interferometric phase shifting and off-axis illumination has been evaluated using the tool. Also, a feature of the CAD Framework which allows representation of a phase shifted mask, together with its layout analysis capability has been used to compact a piece of layout by inserting phase shifted elements into it.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationC. Sengupta, M. Erdelyi, Z. Bor, J. R. Cavallaro, M. C. Smayling, G. Szabo, F. K. Tittel and W. L. Wilson, "An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators," 1996.*
dc.identifier.doihttp://dx.doi.org/10.1117/12.240955en_US
dc.identifier.urihttps://hdl.handle.net/1911/64279
dc.language.isoengen
dc.publisherSPIEen_US
dc.subjectPhotolithographic simulationsen_US
dc.subjectCritical featuresen_US
dc.subjectCAD frameworken_US
dc.titleAn Integrated CAD Framework Linking VLSI Layout Editors and Process Simulatorsen_US
dc.typeConference paperen_US
dc.type.dcmiTexten
dc.type.dcmiTexten_US
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