Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations

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dc.citation.conferenceDate1996en_US
dc.citation.conferenceNameNSF Design and Manufacturing Grantees Conferenceen_US
dc.citation.firstpage345en_US
dc.citation.lastpage346en_US
dc.citation.locationAlbuquerque, NMen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorSengupta, Chaitalien_US
dc.contributor.authorTittel, Frank K.en_US
dc.contributor.authorWilson, William L. Jr.en_US
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-06-21T21:52:55Zen_US
dc.date.available2012-06-21T21:52:55Zen_US
dc.date.issued1996-01-01en_US
dc.description.abstractThis paper describes a CAD tool (An Integrated CAD Framework) which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. The designer can modify the original layout based upon this analysis to create compact circuits with better yield capabilities. The objective of this project is to improve the manufacturability of high density VLSI integrated circuits.en_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipTexas Instrumentsen_US
dc.description.sponsorshipTechnology Modeling Associatesen_US
dc.identifier.citationJ. R. Cavallaro, C. Sengupta, F. K. Tittel and W. L. J. Wilson, "Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations," 1996.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/66.641490en_US
dc.identifier.urihttps://hdl.handle.net/1911/64292en_US
dc.language.isoengen_US
dc.publisherSME Pressen_US
dc.subjectCAD frameworken_US
dc.subjectCircuit designen_US
dc.subjectVLSI layout editorsen_US
dc.subjectIntegrated circuitsen_US
dc.titleAutomated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulationsen_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
dc.type.dcmiTexten_US
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