Rice Wireless

Permanent URI for this collection

https://hdl.handle.net/1911/21945

Formerly the Center for Multimedia Communications, Rice Wireless is part of the university's Electrical and Computer Engineering Department. More information about the group can be found at http://wireless.rice.edu/.

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Now showing 1 - 20 of 268

802.11b Operating in a Mobile Channel: Performance and Challenges
(2003-09-20) Steger, Christopher; Radosavljevic, Predrag; Frantz, Patrick; Center for Multimedia Communications (http://cmc.rice.edu/)
In the past, the worlds of wireless voice and data transmission have been largely disjoint. Voice traffic has been carried over circuit-switched cellular links, and data has been largely restricted to packet-switched wireless LANs. Now, as consumers demand higher bandwidth connections without sacrificing mobility and traffic transitions from primarily voice to data, service providers must produce what is essentially a ubiquitous wireless LAN. To this end, we have studied the effects of a mobile channel on current generation 802.11 A, B, and G wireless LAN cards to see how readily they can be applied to more challenging environments. Not surprisingly, current WLAN technology suffers from significantly degraded performance when subjected to the rigors of a mobile channel. We created emulated bi-directional peer-to-peer links in which we were able to manipulate individual channel parameters. By isolating individual propagation effects and testing several different implementations of the standards, we have discovered which channel parameters have the most significant impact on performance. For instance, the large delay spreads typical of an outdoor channel seem to produce the most deleterious effect on throughput in 802.11b. We use our observations to evaluate the viability of direct-sequence spread-spectrum systems (similar to 802.11b) versus that of OFDM systems (like 802.11a and 802.11g). Then we offer suggestions for how future systems should be adapted in order to manage these effects, and we project the ultimate limitations and possibilities for subsequent 802.11-like systems.
Adaptive Fault Detection and Tolerance for Robots
(TSI Press, 1994-08-01) Visinsky, Monica L.; Cavallaro, Joseph R.; Walker, Ian D.; Center for Multimedia Communication
In existing robot fault detection schemes, sensed values of the joint status (position, velocity, etc.) are typically compared against expected or desired values, and if a given threshold is exceeded, a fault is inferred. The thresholds tend to be empirically determined and held constant over a wide range of trajectories. This leads to false alarms when the threshold is too small to counter the error-inducing effects model inaccuracy and to undetected faults when the threshold is too large for the given situation. This paper presents new methods for adaptively choosing fault detection thresholds, subject to sensing and modeling inaccuracies and the changing status of the robot. Our approach chooses optimal thresholds based on a Singular Value Decomposition (SVD) of a specialized error regressor format of the dynamics to minimize the possibility of false alarms or undtected failures. The thresholds vary dynamically with the changing trajectory and configuration of the robot and with the robot's failure status. Examples of the fault detection scheme for a non-planar 3 DOF robot are given.
Advanced MIMO-CDMA Receiver for Interference Suppression: Algorithms, System-on-Chip Architectures and Design Methodology
(2005-05-01) Guo, Yuanbin; Center for Multimedia Communications (http://cmc.rice.edu/)
MIMO (Multiple Input Multiple Output) technology is proposed in CDMA systems for much higher rate packet services. The receiver architecture is essential for the mobile devices to support high speed multimedia service. The design challenges come from both detection algorithms and hardware architectures. Much more complicated algorithms are required to suppress various interferences. However, the current hardware design archi-tecture and methodology is falling far behind the requirements of small size, low cost and power consumption. System-On-Chip (SoC) architectures are a major revolution taking place in the design of integrated circuits due to many advantages in the power consumption and compact size. The VLSI-oriented complexity reduction of the numerical algorithms plays an essential role to design efficient real-time architectures. Thus, the thesis contributes to three major as-pects: to propose high performance algorithms with realistic complexity in different chan-nel conditions; to propose real-time SoC architectures with area/speed/power efficiency; and to propose an efficient design methodology for modelling, partitioning/binding, verifi-cation and synthesis of the wireless systems. Specifically, to cut the design cycle and enable extensive architecture tradeoff study, an integrated wireless development methodology by High-Level-Synthesis for joint algorithm and architecture optimization is proposed. To address the performance/complexity tradeoff, we propose two LMMSE equalizer algorithms and SoC architectures for different channel conditions. Both an FFT circulant MIMO equalizer and a frequency domain iterative equalizer are proposed to avoid Direct-Matrix-Inverse for the well-conditioned channel as well as long channels working in bad conditions respectively. We then propose a displacement Kalman equalizer with VLSI-oriented architectural optimization for better performance in fast fading environments. For systems with the multi-usersâ signaling, we propose an adaptive Parallel-Residue-Compensation architecture with stage and user spe-cific weights by viewing the multiple transmitter antennas as virtual users to cancel the interferences explicitly. The increased accuracy in interference cancellation leads to signif-icant performance gain over both the complete and partial PIC. The complexity is reduced by using the commonality to avoid the direct interference cancellation. Finally, dynamic power management schemes are proposed to reduce the power consumption in the VLSI architectures using the inherent features of the interference suppression algorithms.
Advanced Techniques for Next-Generation Wireless Systems
(1999-08-20) Sendonaris, Andrew; Center for Multimedia Communications (http://cmc.rice.edu/)
In order to meet the demands of next-generation wireless systems, which will be required to support multirate multimedia at high data rates, it is necessary to employ advanced algorithms and techniques that enable the system to guarantee the quality of service desired by the various media classes. In this work, we present a few novel methods for improving wireless system performance and achieving next-generation goals. Our proposed methods include finding signal sets that are designed for fading channels and support multirate, exploiting knowledge of the fading statistics during the data detection process, exploiting the existence of Doppler in the received signal, and allowing mobile users to cooperate in order to send their information to the base station. We evaluate the performance of our proposed ideas and show that they provide gains with respect to conventional systems. The benefits include multirate support, higher data rates, and more stable data rates. It should be mentioned that, while we focus mainly on a CDMA framework for analyzing our ideas, many of these ideas may also be applied to other wireless system environments.
Analysis of Robots for Hazardous Environments
(IEEE, 1997-01-01) Harpel, Barbara McLaughlin; Dugan, Joanne Bechta; Walker, Ian D.; Cavallaro, Joseph R.; Center for Multimedia Communication
Reliability analysis of fault tolerant systems often ignores the small probability that a failure might not be detected or, if detected, may not be properly handled. The probability that the failure is detected and properly handled is called coverage. Inclusion of coverage in reliability analysis is especially important when analyzing critical systems, systems which for some reason are not easily reparable, or systems whose failure can result in serious damage to the system or its surroundings. One example of a system which can cause such damage is a robot manipulator arm. Robots are being increasingly employed in remote and hazardous environments such as in space and in nuclear waste cleanup, and can exhibit a wild response to subsystem failure, damaging themselves and/or their surroundings. Addition of redundancy to such systems can increase their reliability by allowing continued operation in the presence of faults (provided that the fault is covered), an advantage in a system where repair is difficult or impossible. Coverage models have been used to analyze the behavior of fault-tolerant computer systems in the presence of faults, providing an estimate of the relative probability of an uncovered vs. a covered component failure (given that a fault has occurred) [1]. This paper extends the use of coverage models to the basic components of the joint of a robot and presents data utilizing the calculated coverage for a three-joint robot manipulator arm designed to operate in the plane.
Analyzing Dynamics and Stimulus Feature Dependence in the Information Processing of Crayfish Sustaining Fibers
(2002-04-20) Rozell, Chris; Center for Multimedia Communications (http://cmc.rice.edu/); Digital Signal Processing (http://dsp.rice.edu/); CITI (http://citi.rice.edu/)
The sustaining fiber (SF) stage of the crayfish visual system converts analog stimulus representations to spike train signals. A recent theory quantifies a system's information processing capabilities and relates to statistical signal processing. To analyze SF responses to light stimuli, we extend a wavelet-based algorithm for separating analog input signals and spike output waveforms in composite intracellular recordings. We also present a time-varying RC circuit model to capture nonstationary membrane noise spectral characteristics. In our SF anlysis, information transfer ratios are generally on the order of (10^-4). The SF information processing dynamics show transient peaks followed by decay to steady-state values. A simple theoretical spike generator is analyzed analytically and shows general dynamic and steady-state properties similar to SFs. The information transfer ratios increase with spike rate and dynamic properties are due to direct spike generator dependence on input changes.
Antenna Arrays for Wireless CDMA Communication Systems
(1997-05-20) Madyastha, Raghu; Center for Multimedia Communications (http://cmc.rice.edu/)
The estimation of code delays along with amplitudes and phases of different users constitutes the first stage in the demodulation process in a CDMA communication system. The delay estimation stage is termed the acquisition stage and forms the bottleneck for the detection of users' bitstreams; accurate detection necessitates accurate acquisition. Most existing schemes incorporate a single sensor at the receiver, which leads to an inherent limit in the acquisition based capacity, which is the number of users that can be simultaneously acquired. In this thesis we combine the benefits of spatial processing in the form of an antenna array at the receiver along with code diversity to gain an increase in the capacity of the system. An additional parameter to be estimated now is the direction of arrival (DOA) of each user. We demonstrate the gains in parameter estimation with the incorporation of spatial diversity. We propose two classes of delay-DOA estimation algorithms - a maximum likelihood algorithm and a subspace based algorithm (MUSIC). With reasonable assumptions on the system we are able to derive computationally efficient estimation algorithms and demonstrate the gains achieved in exploiting multiple sensors at the receiver. In addition, we also investigate the benefits of spatial diversity in linear multiuser detection. We consider two linear multiuser detectors, the decorrelating detector and the linear MMSE detector (chosen for their near-far properties) and characterize the performance increase in the multisensor case. We observe that in many cases, the gain can be directly captured in terms of the number of sensors in the array.
Application-Specific Accelerators for Communications
(Springer Science+Business Media, LLC, 2010-01-01) Sun, Yang; Amiri, Kiarash; Brogioli, Michael; Cavallaro, Joseph R.; Center for Multimedia Communication
For computation-intensive digital signal processing algorithms, complexity is exceeding the processing capabilities of general-purpose digital signal processors (DSPs). In some of these applications, DSP hardware accelerators have been widely used to off-load a variety of algorithms from the main DSP host, including FFT, FIR/IIR filters, multiple-input multiple-output (MIMO) detectors, and error correction codes (Viterbi, Turbo, LDPC) decoders. Given power and cost considerations, simply implementing these computationally complex parallel algorithms with high-speed general-purpose DSP processor is not very efficient. However, not all DSP algorithms are appropriate for off-loading to a hardware accelerator. First, these algorithms should have data-parallel computations and repeated operations that are amenable to hardware implementation. Second, these algorithms should have a deterministic dataflow graph that maps to parallel datapaths. The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power. In this chapter, we focus on some of the basic and advanced digital signal processing algorithms for communications and cover major examples of DSP accelerators for communications.
Architecture and Algorithm for a Stochastic Soft-output MIMO Detector
(IEEE, 2007-11-04) Amiri, Kiarash; Radosavljevic, Predrag; Cavallaro, Joseph R.; CMC
In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, and several complexity reduction techniques are proposed to significantly reduce its cost from an architecture-implementation perspective. We also propose an efficient architecture to implement this detector. Finally, this detector is incorporated into an iterative detectiondecoding structure, and through simulations, it is shown that the overall frame error rate (FER) performance and complexity is of the same order as that of the conventional K-best sphere detector.
Architecture and Algorithm for a Stochastic Soft-output MIMO Detector
(IEEE, 2007-11-01) Amiri, Kiarash; Radosavljevic, Predrag; Cavallaro, Joseph R.; Center for Multimedia Communication
In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, and several complexity reduction techniques are proposed to significantly reduce its cost from an architecture-implementation perspective. We also propose an efficient architecture to implement this detector. Finally, this detector is incorporated into an iterative detection-decoding structure, and through simulations, it is shown that the overall frame error rate (FER) performance and complexity is of the same order as that of the conventional K-best sphere detector.
Architecture and Algorithms for Scalable Mobile QoS
(2000-04-20) Sadeghi, Bahareh; Center for Multimedia Communications (http://cmc.rice.edu/)
We develop a simple analytical model to study the system and illustrate several key components of the approach. We formulate the problem of how to group the cells to form the virtual system as an optimization problem and propose a heuristic adaptive clustering algorithm as its solution. Finally, we perform simulations in a two-dimensional network to compare the performance obtained with VBC and adaptive clustering with alternate schemes, including the optimal offline algorithm.
ARCHITECTURE DESIGN AND IMPLEMENTATION OF THE INCREASING RADIUS - LIST SPHERE DETECTOR ALGORITHM
(IEEE, 2009-04-01) Myllylä, Markus; Juntti, Markku; Cavallaro, Joseph R.; Center for Multimedia Communication
A list sphere detector (LSD) is an enhancement of a sphere detector (SD) that can be used to approximate the optimal MAP detector. In this paper, we introduce a novel architecture for the increasing radius (IR)-LSD algorithm, which is based on the Dijkstra’s algorithm. The parallelism possibilities are introduced in the presented architecture, which is also scalable for different multiple-input multiple-output (MIMO) systems. The novel architecture is implemented on a Virtex-IV field programmable gate array (FPGA) chip using high-level ANSI C++ language based Catapult C Synthesis tool from Mentor Graphics. The used word lengths, the latency of the design, and the required resources are presented and analyzed for 4 x 4 MIMO system with 16- quadrature amplitude modulation (QAM). The detector implementation achieves a maximum throughput of 12.1Mbps at high signal-to-noise ratio (SNR).
Architecture Design and Implementation of the Metric First List Sphere Detector Algorithm
(IEEE, 2011-05-01) Myllylä, Markus; Cavallaro, Joseph R.; Juntti, Markku; Center for Multimedia Communication
Soft-output detection of a multiple-input–multiple-output (MIMO) signal pose a significant challenge in future wireless systems. In this paper, we introduce a soft-output modified metric first (MMF)-LSD algorithm for MIMO detection. We design a scalable architecture and address a method to decrease memory requirements. We provide implementation results for a spatial multiplexing (SM) system with four transmitted streams and with 16- and 64-quadrature amplitude modulation (QAM) on a 0.18- m CMOS application specific integrated circuit (ASIC) technology. The MFF-LSD implementation is more efficient than the depth first (DF) -LSD in the crucial low signal-to-noise rate (SNR)region and the detection rate of the 64-QAM implementation is 39.2 Mbps@26 db with 48.2 kGEs complexity.
Architectures for Cognitive Radio Testbeds and Demonstrators – An Overview
(IEEE, 2010-06-01) Gustafsson, Oscar; Amiri, Kiarash; Andersson, Dennis; Blad, Anton; Bonner, Christian; Cavallaro, Joseph R.; Declerck, Jeroen; Dejonghe, Antoine; Eliardsson, Patrik; Glasse, Miguel; Hayar, Aawatif; Hollevoet, Lieven; Hunter, Chris; Joshi, Madhura; Kaltenberger, Florian; Knopp, Raymond; Le, Khanh; Miljanic, Zoran; Murphy, Patrick; Naessens, Frederik; Nikaein, Navid; Nussbaum, Dominique; Pacalet, Renaud; Raghavan, Praveen; Sabharwal, Ashutosh; Sarode, Onkar; Spasojevic, Predrag; Sun, Yang; Tullberg, Hugo M.; Vander Aa, Tom; Van der Perre, Liesbet; Wetterwald, Michelle; Wu, Michael; Center for Multimedia Communication
Wireless communication standards are developed at an ever-increasing rate of pace, and significant amounts of effort is put into research for new communication methods and concepts. On the physical layer, such topics include MIMO, cooperative communication, and error control coding, whereas research on the medium access layer includes link control, network topology, and cognitive radio. At the same time, implementations are moving from traditional fixed hardware architectures towards software, allowing more efficient development. Today, field-programmable gate arrays (FPGAs) and regular desktop computers are fast enough to handle complete baseband processing chains, and there are several platforms, both open-source and commercial, providing such solutions. The aims of this paper is to give an overview of five of the available platforms and their characteristics, and compare the features and performance measures of the different systems.
Architectures for Heterogeneous Multi-Tier Networks
(2002-01-15) Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
Next-generation wireless computing platforms will contain flexible communications capabilites. At Rice University, the Rice Everywhere NEtwork (RENE) project is investigating a multi-standard, multi-tier integration of W-CDMA cellular systems, high speed wireless LANs, and home wireless networks. There are many challenges in mapping these advanced communication algorithms to real-time hardware computing platforms. In this paper, we present current work on the development of a reconfigurable baseband physical layer containing DSP processors and FPGA accelerators. Our goal is the design of a multi-tier network interface card (mNIC) which is capable of exploiting eÂ±cient, low-power reconfiguration.
Arithmetic Acceleration Techniques for Wireless Communication Receivers
(1999-10-20) Das, Suman; Rajagopal, Sridhar; Sengupta, Chaitali; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
We develop techniques to accelerate the implementation of the next generation wireless communication algorithms in hardware. We discuss an implementation of a key computationally intensive baseband algorithm for joint multiuser channel estimation and detection for this purpose and study its real-time requirements. An analysis of the bottlenecks present in the algorithm is made. We present an acceleration technique using task decomposition to take advantage of the existing pipelining and parallelism flow in the algorithm. We show that an application specific system design with multiple processing elements is more effective than the conventional single processor approach as it can satisfy the high data rate requirements of the next generation wireless communication systems. Our analysis is done independent of the final mapping of the processing elements in hardware.
ASIC Implementation Comparison of SIC and LSD Receivers for MIMO-OFDM
(IEEE, 2008-10-01) Ketonen, Johanna; Myllylä, Markus; Juntti, Markku; Cavallaro, Joseph R.; Center for Multimedia Communication
MIMO-OFDM receivers with horizontal encoding are considered in this paper. The successive interference cancellation (SIC) algorithm is compared to the K-best list sphere detector (LSD). A modification to the K-best LSD algorithm is introduced. The SIC and K-best LSD receivers are designed for a 2 x 2 antenna system with 64-quadrature amplitude modulation (QAM). The ASIC implementation results for both architectures are presented. The K-best LSD outperforms the SIC receiver in bad channel conditions but the SIC receiver performs better in channels with less correlated MIMO streams. The latency of the K-best LSD is large due to the high modulation order and list size. The throughput of the SIC receiver is more than 6 times higher than that of the K-best LSD.
Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations
(SME Press, 1996-01-01) Cavallaro, Joseph R.; Sengupta, Chaitali; Tittel, Frank K.; Wilson, William L. Jr.; Center for Multimedia Communication
This paper describes a CAD tool (An Integrated CAD Framework) which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. The designer can modify the original layout based upon this analysis to create compact circuits with better yield capabilities. The objective of this project is to improve the manufacturability of high density VLSI integrated circuits.
Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations
(IEEE, 1997-11-01) Sengupta, Chaitali; Cavallaro, Joseph R.; Wilson, William L.; Tittel, Frank K.; Center for Multimedia Communication
In this paper, we address the problem of identifying and evaluating “critical features” in an integrated circuit (IC) layout. The “critical features” (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying “critical features” in a layout and then evaluate the “critical features” using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (an Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates “critical features”
Baseband Architecture Design for Future Wireless Base-Station Receivers
(2000-05-20) Rajagopal, Sridhar; Center for Multimedia Communications (http://cmc.rice.edu/)
This thesis demonstrates designing efficient algorithms and architectures to meet the real-time requirements of future wireless base-station receivers. Next generation receivers require orders-of-magnitude performance improvements in order to provide support for features such as Multimedia, Quality-Of-Service and extremely high data rates. The sophisticated, compute-intensive algorithms proposed to integrate these features make their real-time implementation difficult on current DSP-based receivers. A real-time implementation can be achieved by (1.) making the algorithms computationally efficient, without significant loss in error rate performance, (2.) task partitioning, and (3.) designing hardware to exploit available pipelining, parallelism and bit-level computations. Multiuser Channel Estimation and Detection, two of the most compute-intensive baseband tasks in the receiver, are studied on DSPs for performance evaluation. A reduced complexity iterative channel estimation scheme for slow fading channels is proposed for a fixed point, area-time efficient and real-time VLSI architecture. The multiuser detection algorithm is modified for a simple, pipelined structure. A GPP or DSP based architecture with reconfigurable support suited for wireless communications is proposed and extensions are developed to accelerate the implementation of wireless communication algorithms.

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