R-3 Repository :: Browsing by Author "Mohanram, Kartik"

Browsing by Author "Mohanram, Kartik"

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Ambipolar electronics
(2010) Yang, Xuebei; Mohanram, Kartik
Ambipolar conduction, characterized by a superposition of electron and hole currents, has been observed in many next-generation devices including carbon nanotube, graphene, silicon nanowire, and organic transistors. This paper describes exciting new design opportunities in both analog and digital domains, all of which are inspired by the ability to control ambipolarity during circuit operation. We illustrate this with (i) a single-transistor polarity controllable amplifier, which can greatly simplify communication circuits and (ii) polarity controllable ambipolar logic gates, which are highly expressive yet compact compared to conventional CMOS.
Approximate logic circuits: Theory and applications
(2011) Choudhury, Mihir Rajanikant; Mohanram, Kartik
CMOS technology scaling, the process of shrinking transistor dimensions based on Moore's law, has been the thrust behind increasingly powerful integrated circuits for over half a century. As dimensions are scaled to few tens of nanometers, process and environmental variations can significantly alter transistor characteristics, thus degrading reliability and reducing performance gains in CMOS designs with technology scaling. Although design solutions proposed in recent years to improve reliability of CMOS designs are power-efficient, the performance penalty associated with these solutions further reduces performance gains with technology scaling, and hence these solutions are not well-suited for high-performance designs. This thesis proposes approximate logic circuits as a new logic synthesis paradigm for reliable, high-performance computing systems. Given a specification, an approximate logic circuit is functionally equivalent to the given specification for a "significant" portion of the input space, but has a smaller delay and power as compared to a circuit implementation of the original specification. This contributions of this thesis include (i) a general theory of approximation and efficient algorithms for automated synthesis of approximations for unrestricted random logic circuits, (ii) logic design solutions based on approximate circuits to improve reliability of designs with negligible performance penalty, and (iii) efficient decomposition algorithms based on approxiiii mate circuits to improve performance of designs during logic synthesis. This thesis concludes with other potential applications of approximate circuits and identifies. open problems in logic decomposition and approximate circuit synthesis.
Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits
(IEEE, 2011-03) Rostami, Masoud; Mohanram, Kartik
This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.
Graphene Ambipolar Multiplier Phase Detector
(IEEE, 2011-10) Yang, Xuebei; Liu, Guanxiong; Rostami, Masoud; Balandin, Alexander A.; Mohanram, Kartik
We report the experimental demonstration of a multiplier phase detector implemented with a single top-gated graphene transistor. Ambipolar current conduction in graphene transistors enables simplification of the design of the multiplier phase detector and reduces its complexity in comparison to phase detectors based on conventional unipolar transistors. Fabrication of top-gated graphene transistors is essential to achieve the higher gain necessary to demonstrate phase detection. We report a phase detector gain of −7 mV/rad in this letter. An analysis of key technological parameters of the graphene transistor, including series resistance, top-gate insulator thickness, and output resistance, indicates that the phase detector gain can be improved by as much as two orders of magnitude.
Logic design for reliability
(2008) Choudhury, Mihir; Mohanram, Kartik
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology alternatives. Scaling of CMOS devices below 100nm has revealed their vulnerability to process variations, thermodynamic variations, transient errors due to radiation, electromagnetic interference and extreme scaling effects. Variations cause the output of gates to deviate from the correct value potentially leading to logic errors. The search for new devices to replace CMOS in the future has led to advances in the synthesis and self-assembly of nanoelectronic devices like carbon nanotube transistors that indicate the ability to manufacture dense nanoelectronic fabrics. However, the tremendous device densities afforded by nanoelectronic technologies is expected to be accompanied by substantial increases in defect densities, transient error rates, and performance variability. Thus, high failure rates are inherent to computing devices of the future and have led to an increased interest in investigating the potential of logic design techniques to improve circuit reliability. This thesis contributes to two major aspects of logic design for circuit reliability: (1) Computing the reliability of logic circuits built with unreliable devices. (2) Detection of errors in logic circuits based on approximate logic functions.
Novel dual-threshold voltage FinFETs for circuit design and optimization
(2011) Rostami, Masoud; Mohanram, Kartik
A great research effort has been invested on finding alternatives to CMOS that have better process variation and subthreshold leakage. From possible candidates, FinFET is the most compatible with respect to CMOS and it has shown promising leakage and speed performance. This thesis introduces basic characteristics of FinFETs and the effects of FinFET physical parameters on their performance are explained quantitatively. I show how dual- V th independent-gate FinFETs can be fabricated by optimizing their physical parameters. Optimum values for these physical parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-14, FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than CMOS gates. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz and 75°C, the library that contains the novel gates reduces total power and the number of fins by 36% and 37% respectively, over a conventional library that does not have novel gates in the 32nm technology.
Novel dual-Vth independent-gate FinFET circuits
(IEEE, 2010) Rostami, Masoud; Mohanram, Kartik
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology.
Reliability-driven circuit optimization and design
(2007) Zhou, Quming; Mohanram, Kartik
Single-event upsets (SEUs) induced by high-energy neutrons and alpha particles have emerged as a key reliability threat to advanced commercial electronic components and systems. This dissertation describes gate-level radiation hardening techniques to improve the reliability of combinational circuits to SEUs. Such techniques have several advantages including low overhead, compatibility with the standard design flow, and enhancing classical fault avoidance and tolerance techniques. This dissertation begins by discussing the characteristics of SEUs in combinational circuits that can be used to improve circuit robustness. We develop numerical and compact circuit-level models to describe transient effects in circuits. Based on the models, we develop various solutions to successfully meet power-performance constraints for reliability-driven design optimization. The first solution is a rank-and-size approach where the most sensitive gates are sized to increase circuit robustness. To enable better design space exploration, we introduce an SEU constraint alongside traditional design constraints, such as area, power, and performance. This effort leads to new algorithms based on iterative and geometric programming optimizations. We also describe filter insertion in addition to sizing and dual-V DD to reduce the design overhead further. The effectiveness of these approaches is substantiated by experimental results. We describe the advantage and disadvantage of each approach to illustrate the applicability to various situations.
Semi-analytical model for carbon nanotube and graphene nanoribbon transistors
(2010) Yang, Xuebei; Mohanram, Kartik
Carbon nanotubes and graphene provide high carrier mobility for ballistic transport, high carrier velocity for fast switching, and excellent mechanical and thermal conductivity. As a result, they are widely considered as next generation candidate materials for nanoelectronics. In this thesis, I first propose a physics-based semi-analytical model for Schottky-barrier (SB) carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model reduces the computational complexity in the two critical but time-consuming steps, namely the calculation of the tunneling probability and the self-consistent evaluation of the surface potential in the transistor channel. Since SB-type CNT and GNR transistors exhibit ambipolar conduction that is not preferable in digital applications, I further propose a semi-analytical model for the double-gate transistor structure that is able to control the ambipolar conduction in-field. Future directions, including the modeling of new CNT and GNR devices and novel circuits based on the in-field controllability of ambipolar conduction, will also be described.
System and method for context-independent codes for off-chip interconnects
(2011-07-12) Rixner, Scott; Mohanram, Kartik; Choudhury, Mihir R.; Rice University; United States Patent and Trademark Office
A system and method for context-independent coding using frequency-based mapping schemes, sequence-based mapping schemes, memory trace-based mapping schemes, and/or transition statistics-based mapping schemes in order to reduce off-chip interconnect power consumption. State-of-the-art context-dependent, double-ended codes for processor-SDRAM off-chip interfaces require the transmitter and receiver (memory controller and SDRAM) to collaborate using the current and previously transmitted values to encode and decode data. In contrast, the memory controller can use a context-independent code to encode data stored in SDRAM and subsequently decode that data when it is retrieved, allowing the use of commodity memories. A single-ended, context-independent code is realized by assigning limited-weight codes using a frequency-based mapping technique. Experimental results show that such a code can reduce the power consumption of an uncoded off-chip interconnect by an average of 30% with less than a 0.1% degradation in performance.

Browsing by Author "Mohanram, Kartik"

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