Browsing by Author "Jones, Bryan Allen"

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    Rapid Prototyping of Wireless Communications Systems
    (2002-05-20) Jones, Bryan Allen; Center for Multimedia Communications (http://cmc.rice.edu/)
    This thesis introduces rapid prototyping methodology which overcomes important barriers in the design and implementation of digital signal processing (DSP) algorithms and systems on embedded hardware platforms, such as cellular phones. This thesis describes rapid prototyping in terms of a simulation/prototype bridge and in terms of appropriate language design. The simulation/prototype bridge combines the strengths of simulation and of prototyping, allowing the designer to develop and evaluate next-generation communications systems partly in simulation on a host computer, and partly as a prototype on embedded hardware. Appropriate language design allows engineers to express a communications system as a block diagram, in which each block represents an algorithm specified by a set of equations. Software tools developed for this thesis implement both concepts, and have been successfully used in the development of a type-based detector for a code-division multiple access (CDMA) cellular wireless communications system.
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    Real-Time DSP Multiprocessor Implementation for Future Wireless Base-Station Receivers
    (2000-08-20) Jones, Bryan Allen; Rajagopal, Sridhar; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    The convergence of cellular phones, the Internet, and laptop computers into a single small, lightweight, wireless information appliance drives a need for a high data rate, low-power digital wireless communication link to enable the creation of such a device. A simulation environment supporting rapid prototyping is developed, and used to evaluate the real-time data-rate performance of these receivers implemented on a multiprocessor DSP board. Simulations of a multiprocessor implementation of joint multiuser channel estimation and detection algorithms is projected to achieve combined perform-ance of 15.6 Kb/user/sec for 10 users. Performance gains over a single-processor implementation range from 5% for the three-user case to 69% for a 15 user case.
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    Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs
    (2000-10-20) Rajagopal, Sridhar; Jones, Bryan Allen; Cavallaro, Joseph R.; Center for Multimedia Communications (http://cmc.rice.edu/)
    This paper presents a multiprocessor solution to meet real-time requirements of implementing advanced algorithms for multiuser channel estimation and detection for third and fourth generation wireless base-station receivers. We identify the key bottlenecks in the algorithms and task-partition the algorithms on multiple processors. We get speedups, ranging from 1.19X to 5.92X for a dual-DSP implementation due to both additional computational power and additional internal memory compared to a single DSP implementation using external memory. We also identify parts of the algorithm that exhibit bit-level parallelism, not utilized by DSPs. FPGAs can then be used to accelerate these parts and meet real-time requirements of 128 Kbps for next generation wireless systems.
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    W-CDMA real-time algorithm implementation and evaluation
    (2000-05-20) Jones, Bryan Allen; Center for Multimedia Communications (http://cmc.rice.edu/)
    This paper describes a platform to enable and explore the design and implementation of next-generation CDMA wireless base stations. A DSP and FPGA-based multiprocessor board is integrated into a Simulink-based wireless testbed environment, providing the ability to simulate the behavior and performance of new algorithms. Performance measurements are taken and analyzed, demonstrating key areas for algorithm improvement.