Browsing by Author "Giles, Ellis Robinson"
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Item Hardware Transactional Persistent Memory(2019-01-31) Giles, Ellis Robinson; Varman, PeterRecent years have witnessed a sharp shift towards real-time data-driven and high-throughput applications, impelled by pervasive multi-core architectures and parallel programming models. This shift has spurred a broad adoption of in-memory databases and massively-parallel transaction processing across scientific, business, and industrial application domains. However, these applications are severely handicapped by the difficulties in maintaining persistence on typical durable media like hard-disk drives (HDDs) and solid-state drives (SSDs) without sacrificing either performance or reliability. The ending of Moore's Law and Dennard Scaling have further slowed performance gains and scalability of these applications. Two emerging hardware developments hold enormous promise for transformative gains in both speed and scalability of concurrent data-intensive applications. The first is the arrival of Persistent Memory, or PM, a generic term for byte-addressable non-volatile memories, such as Intel's 3D XPoint technology. The second is the availability of CPU-based transaction support known as Hardware Transactional Memory, or HTM, which makes it easier for applications to exploit multi-core concurrency without the need for expensive lock-based software. This thesis introduces Hardware Transactional Persistent Memory, the first union of HTM with PM without any changes to known processor designs or protocols, allowing for high-performance, concurrent, and durable transactions. The techniques presented are supported on three pillars: handling uncontrolled cache evictions from the processor cache hierarchy, logging to resist failure during persistent memory updates, and transaction ordering to permit consistent recovery from a machine crash. We develop pure software solutions that work with existing processor architectures as well as software-assisted solutions that exploit external memory controller hardware support. The thesis also introduces the notion of relaxed versus strict durability, allowing individual applications to tradeoff performance against robustness, while guaranteeing recovery to a consistent system state.Item WrAP: Hardware and Software Support for Atomic Persistence in Storage Class Memory(2015-04-23) Giles, Ellis Robinson; Varman, Peter J.; Cavallaro, Joseph R; Jermaine, Christoper MIn-memory computing is gaining popularity as a means of sidestepping the performance bottlenecks of traditional block-based storage devices. However, the volatile nature of DRAM makes these systems vulnerable to system crashes, while the need to continuously refresh massive amounts of passive memory-resident data increases power consumption. Emerging storage-class memory (SCM) technologies, like Phase Change Memory and Memristors, combine fast DRAM-like cache-line access granularity with the persistence of storage devices like disks or SSDs, resulting in potential 10x - 100x performance gains, and low passive power consumption. This unification of storage and memory into a single directly-accessible persistent storage tier is a mixed blessing, as it pushes upon developers the burden of ensuring that SCM stores are ordered correctly, flushed from processor caches, and if interrupted by sudden machine stoppage, not left in inconsistent states. The complexity of ensuring properly ordered and all-or-nothing updates is addressed in this thesis in both a software-hardware architecture and a software-only based solution. This thesis extends and evaluates a software-hardware architecture called WrAP, or Write-Aside Persistence, for atomic stores to SCM. This thesis also presents SoftWrAP, a library for Software based Write-Aside Persistence, which provides lightweight atomicity and durability for SCM storage transactions. Both methods are shown to provide atomicity and durability while simultaneously ensuring that fast paths through the cache, DRAM, and persistent memory layers are not slowed down by burdensome buffering or double-copying requirements. Software-hardware architecture evaluation of trace-driven simulation of transactional data structures indicates the potential for significant performance gains using the WrAP approach. The SoftWrAP library is evaluated with both handcrafted SCM- based micro-benchmarks as well as existing applications, specifically the STX B+Tree library and SQLite database, backed by emulated SCM. Our results show the ease of using the API to create atomic persistent regions and the significant benefits of SoftWrAP over existing methods such as undo logging and shadow copying. SoftWrAP can match non-atomic durable writes to SCM, thereby gaining atomic consistency almost for free.