Computer Science Technical Reports

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Browsing Computer Science Technical Reports by Author "Alkabani, Yousra"

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    A Timing Channel Spyware Robust to MAC Random Back-off
    (2010-03-02) Alkabani, Yousra; Coleman, Todd; Kiyavash, Negar; Koushanfar, Farinaz
    This paper presents the design and implementation of spyware communication circuits built into the widely used Carrier Sense Multiple Access with collision avoidance (CSMA/CA) protocol. The spyware components are embedded within the sequential and combinational communication circuit structure during synthesis, rendering the distinction or dissociation of the spyware from the original circuit impossible. We take advantage of the timing channel resulting from transmission of packets to implement a new practical coding scheme that covertly transfers the spied data. Our codes are robust against the CSMA/CA’s random retransmission time for collision avoidance and in fact take advantage of it to disguise the covert communication. The data snooping may be sporadically triggered, either externally or internally. The occasional trigger and the real-time traffic’s variability make the spyware timing covert channel detection a challenge. The spyware is implemented and tested on a widely used open-source wireless CSMA/CA radio platform. We identify the following performance metrics and evaluate them on our architecture: 1) efficiency of implementation of the encoder; 2) robustness of the communication scheme to heterogeneous CSMA/CA effects; and 3) difficulty of covert channel detection. We evaluate criterion 1) completely theoretically. Criterion 2) is evaluated by simulating a wireless CSMA/CA architecture and testing the robustness of the decoder in different heterogeneous wireless conditions. Criterion 3) is confirmed experimentally using the state-of-the-art covert timing channel detection methods.
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    A Unified Framework for Multimodal IC Trojan Detection
    (2010-02-02) Alkabani, Yousra; Koushanfar, Farinaz; Mirhoseini, Azalia
    This paper presents a unified formal framework for integrated circuits (IC) Trojan detection that can simultaneously employ multiple noninvasive measurement types. Hardware Trojans refer to modifications, alterations, or insertions to the original IC for adversarial purposes. The new framework formally defines the IC Trojan detection for each measurement type as an optimization problem and discusses the complexity. A formulation of the problem that is applicable to a large class of Trojan detection problems and is submodular is devised. Based on the objective function properties, an efficient Trojan detection method with strong approximation and optimality guarantees is introduced. Signal processing methods for calibrating the impact of inter-chip and intra-chip correlations are presented. We define a new sensitivity metric which formally quantifies the impact of modifications to each gate on the Trojan detection. Using the new metric, we compare the Trojan detection capability of the different measurement types for static (quiescent) current, dynamic (transient) current, and timing (delay) measurements. We propose a number of methods for combining the detections of the different measurement types and show how the sensitivity results can be used for a systematic combining of the detection results. Experimental evaluations on benchmark designs reveal the low-overhead and effectiveness of the new Trojan detection framework and provides a comparison of different detection combining methods.
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    Input vector control for post-silicon leakage current minimization under manufacturing variations
    (2008-02-04) Alkabani, Yousra; Koushanfar, Farinaz; Massey, Tammara; Potkonjak, Miodrag
    We present the first approach for post-silicon leakage power reduction through input vector control (IVC) that takes into account the impact of the manufacturing variability (MV). Because of the MV, the integrated circuits (ICs) implementing one design require different input vectors to achieve their lowest leakage states. There are two major challenges that have to be addressed. The first is the extraction of the gate-level characteristics of an IC by measuring only the overall leakage power for different inputs. The second problem is the rapid generation of input vectors that result in a low leakage for a large number of unique ICs that implement a given design, but are different in the post-manufacturing phase. We solve the first problem using a linear programming formulation that in a polynomial time, finds the most likely gate-level characterization of a pertinent IC. The approach is provably optimal, if there are no measurement errors; we also examine the erroneous cases. We address the second problem using the coordinated application of statistical clustering and the very large neighborhood iterative improvement algorithm. Experimental results on a large set of benchmark instances demonstrate the efficiency of the proposed methods. For example, the leakage power consumption could be reduced in average by more than 10.4%, when compared to the previously published IVC techniques that did not consider MV.