Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis
| dc.citation.conferenceDate | 2009 | en_US |
| dc.citation.conferenceName | IEEE International System-on-Chip (SOC) Conference | en_US |
| dc.citation.firstpage | 267 | en_US |
| dc.citation.lastpage | 270 | en_US |
| dc.citation.location | Belfast, Northern Ireland | en_US |
| dc.contributor.author | Sun, Yang | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.author | Ly, Tai | en_US |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-11T20:51:00Z | en_US |
| dc.date.available | 2012-06-11T20:51:00Z | en_US |
| dc.date.issued | 2009-09-01 | en_US |
| dc.description.abstract | This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential untimed C algorithm. We propose two parallel LDPC decoder architectures: (1) per-layer decoding architecture with scalable parallelism, and (2) multi-layer pipelined decoding architecture to achieve higher throughput. Based on the PICO technology, we have implemented a two-layer pipelined decoder on a TSMC 65nm 0.9V 8-metal layer CMOS technology with a core area of 1.2 mm2. The maximum achievable throughput is 415 Mbps when operating at 400 MHz clock frequency and the estimated peak power consumption is 180 mW. | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | Nokia Siemens Networks (NSN) | en_US |
| dc.description.sponsorship | Xilinx | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | Y. Sun, J. R. Cavallaro and T. Ly, "Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis," 2009. | en_US |
| dc.identifier.doi | http://dx.doi.org/10.1109/SOCCON.2009.5398044 | en_US |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=3715157293471594724&hl=en&as_sdt=0,44 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/64237 | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | LDPC decoder | en_US |
| dc.subject | CMOS | en_US |
| dc.subject | High level synthesis | en_US |
| dc.subject | PICO | en_US |
| dc.title | Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
| dc.type.dcmi | Text | en_US |