A systolic VLSI architecture for complex SVD
| dc.contributor.advisor | Cavallaro, Joseph R. | en_US |
| dc.creator | Hemkumar, Nariankadu Datatreya | en_US |
| dc.date.accessioned | 2009-06-04T00:35:17Z | en_US |
| dc.date.available | 2009-06-04T00:35:17Z | en_US |
| dc.date.issued | 1991 | en_US |
| dc.description.abstract | This thesis presents a systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with "parallel ordering". As a basic step in the algorithm, a two-step, two-sided unitary transformation scheme is employed to diagonalize a complex 2 $\times$ 2 matrix. The transformations are tailored to the use of CORDIC (COordinate Rotation DIgital Computer) algorithms for high speed arithmetic. The complex SVD array is modeled on the Brent-Luk-VanLoan array for real SVD. An array with O($n\sp2$) processors is required to compute the SVD of a $n \times n$ matrix in O(n log n) time. An architecture for the complex 2 $\times$ 2 processor with an area complexity twice that of a real 2 $\times$ 2 processor, is shown to have the best area/time tradeoff for VLSI implementation. Despite the involved nature of computations on complex data, the computation time for the complex SVD array is less than three times that for a real SVD array with a similar CORDIC based implementation. | en_US |
| dc.format.extent | 122 p. | en_US |
| dc.format.mimetype | application/pdf | en_US |
| dc.identifier.callno | Thesis E.E. 1991 Hemkumar | en_US |
| dc.identifier.citation | Hemkumar, Nariankadu Datatreya. "A systolic VLSI architecture for complex SVD." (1991) Master’s Thesis, Rice University. <a href="https://hdl.handle.net/1911/13526">https://hdl.handle.net/1911/13526</a>. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/13526 | en_US |
| dc.language.iso | eng | en_US |
| dc.rights | Copyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder. | en_US |
| dc.subject | Electronics | en_US |
| dc.subject | Electrical engineering | en_US |
| dc.subject | Computer science | en_US |
| dc.title | A systolic VLSI architecture for complex SVD | en_US |
| dc.type | Thesis | en_US |
| dc.type.material | Text | en_US |
| thesis.degree.department | Electrical Engineering | en_US |
| thesis.degree.discipline | Engineering | en_US |
| thesis.degree.grantor | Rice University | en_US |
| thesis.degree.level | Masters | en_US |
| thesis.degree.name | Master of Science | en_US |
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