A Massively Parallel Implementation of QC-LDPC Decoder on GPU
| dc.citation.conferenceDate | 2011 | en_US |
| dc.citation.conferenceName | IEEE 9th Symposium on Application Specific Processors (SASP) | en_US |
| dc.citation.firstpage | 82 | en_US |
| dc.citation.lastpage | 85 | en_US |
| dc.citation.location | San Diego, CA | en_US |
| dc.contributor.author | Wang, Guohui | en_US |
| dc.contributor.author | Wu, Michael | en_US |
| dc.contributor.author | Sun, Yang | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communication | en_US |
| dc.date.accessioned | 2012-06-06T20:59:03Z | en_US |
| dc.date.available | 2012-06-06T20:59:03Z | en_US |
| dc.date.issued | 2011-06-01 | en_US |
| dc.description.abstract | The graphics processor unit (GPU) is able to provide a low-cost and flexible software-based multi-core architecture for high performance computing. However, it is still very challenging to efficiently map the real-world applications to GPU and fully utilize the computational power of GPU. As a case study, we present a GPU-based implementation of a real-world digital signal processing (DSP) application: low-density parity-check (LDPC) decoder. The paper shows the efforts we made to map the algorithm onto the massively parallel architecture of GPU and fully utilize GPU’s computational resources to significantly boost the performance. Moreover, several efficient data structures have been proposed to reduce the memory access latency and the memory bandwidth requirement. Experimental results show that the proposed GPU-based LDPC decoding accelerator can take advantage of the multi-core computational power provided by GPU and achieve high throughput up to 100.3Mbps. | en_US |
| dc.description.sponsorship | Renesas Mobile | en_US |
| dc.description.sponsorship | Texas Instruments | en_US |
| dc.description.sponsorship | Xilinx | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | G. Wang, M. Wu, Y. Sun and J. R. Cavallaro, "A Massively Parallel Implementation of QC-LDPC Decoder on GPU," 2011. | en_US |
| dc.identifier.doi | http://dx.doi.org/10.1109/SASP.2011.5941084 | en_US |
| dc.identifier.other | http://scholar.google.com/scholar?cluster=16007718846675224041&hl=en&as_sdt=0,44&as_vis=1 | en_US |
| dc.identifier.other | 10.1109/SASP.2011.5941084 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/64229 | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | GPU | en_US |
| dc.subject | Parallel computing | en_US |
| dc.subject | CUDA | en_US |
| dc.subject | LDPC decoder | en_US |
| dc.title | A Massively Parallel Implementation of QC-LDPC Decoder on GPU | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
| dc.type.dcmi | Text | en_US |