A reconfigurable viterbi decoder architecture
| dc.citation.bibtexName | inproceedings | en_US |
| dc.citation.conferenceName | Asilomar Conference on Signals, Systems, and Computers | en_US |
| dc.citation.firstpage | 66 | en_US |
| dc.citation.lastpage | 71 | en_US |
| dc.citation.volumeNumber | 1 | en_US |
| dc.contributor.author | Chadha, Kanu | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.org | Center for Multimedia Communications (http://cmc.rice.edu/) | en_US |
| dc.date.accessioned | 2007-10-31T00:38:33Z | en_US |
| dc.date.available | 2007-10-31T00:38:33Z | en_US |
| dc.date.issued | 2001-11-20 | en_US |
| dc.date.modified | 2003-11-09 | en_US |
| dc.date.note | 2002-04-17 | en_US |
| dc.date.submitted | 2001-11-20 | en_US |
| dc.description | Conference Paper | en_US |
| dc.description.abstract | We present the design and implementation of a novel reconfigurable Viterbi decoder which provides dynamic adaptation to different constraint length and code rate convolutional codes. A decoder what supports constraint lengths from 3-7, and code rates ½-1/3 has been synthesized on an FPGA. With a throughput of 20 Mbps, the proposed decoder is suitable for use in receiver architectures of the 802.11a wireless local area network and 3G cellular code division multiple access environments. Results show that the area overhead associated with such a reconfigurable implementation as compared to a fixed constraint length 7 implementation is just 2.9%. | en_US |
| dc.description.sponsorship | Texas Advanced Technology Program | en_US |
| dc.description.sponsorship | Nokia | en_US |
| dc.description.sponsorship | National Science Foundation | en_US |
| dc.identifier.citation | K. Chadha and J. R. Cavallaro, "A reconfigurable viterbi decoder architecture," vol. 1, 2001. | en_US |
| dc.identifier.doi | http://dx.doi.org/10.1109/ACSSC.2001.986882 | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/19764 | en_US |
| dc.language.iso | eng | en_US |
| dc.subject | viterbi decoder architecture | en_US |
| dc.subject.keyword | viterbi decoder architecture | en_US |
| dc.title | A reconfigurable viterbi decoder architecture | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |
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