Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers

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dc.citation.bibtexNamearticleen_US
dc.citation.firstpage143
dc.citation.issueNumber2en_US
dc.citation.journalTitleJournal of VLSI Signal Processingen_US
dc.citation.lastpage156
dc.citation.volumeNumber31en_US
dc.contributor.authorRajagopal, Sridharen_US
dc.contributor.authorBhashyam, Srikrishnaen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.authorAazhang, Behnaamen_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:59:06Z
dc.date.available2007-10-31T00:59:06Z
dc.date.issued2002-06-20en
dc.date.modified2001-09-18en_US
dc.date.submitted2001-09-18en_US
dc.descriptionJournal Paperen_US
dc.description.abstractThis paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband processing operations in wireless base-station receivers for CDMA. Future wireless base-station receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP implementations of these algorithms are unable to meet real-time requirements. However, there exists massive parallelism and bit level arithmetic present in these algorithms than can be revealed and efficiently implemented in a VLSI architecture. We <i>it re-design</i> an existing channel estimation algorithm from an implementation perspective for a reduced complexity, fixed-point hardware implementation. Fixed point simulations are presented to evaluate the precision requirements of the algorithm. A dependence graph of the algorithm is presented and area-time trade-offs are developed. An area-constrained architecture achieves low data rates with minimum hardware, which may be used in pico-cell base-stations. A time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data processing rates. An area-time efficient architecture meets real-time requirements with minimum area overhead.en_US
dc.description.sponsorshipTexas Advanced Technology Programen_US
dc.description.sponsorshipTexas Instrumentsen_US
dc.description.sponsorshipNokiaen_US
dc.identifier.citationS. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers," <i>Journal of VLSI Signal Processing,</i> vol. 31, no. 2, 2002.
dc.identifier.doihttp://dx.doi.org/10.1023/A:1015393322264en_US
dc.identifier.urihttps://hdl.handle.net/1911/20224
dc.language.isoeng
dc.publisherKluwer Academic Pubishersen_US
dc.subjectreal-time implementation*
dc.subjectmultiuser channel estimation*
dc.subjectVLSI*
dc.subjectdependence graphs*
dc.subjectDSP*
dc.subjectW-CDMA*
dc.subjectfixed-point*
dc.subject.keywordreal-time implementationen_US
dc.subject.keywordmultiuser channel estimationen_US
dc.subject.keywordVLSIen_US
dc.subject.keyworddependence graphsen_US
dc.subject.keywordDSPen_US
dc.subject.keywordW-CDMAen_US
dc.subject.keywordfixed-pointen_US
dc.titleEfficient VLSI architectures for multiuser channel estimation in wireless base-station receiversen_US
dc.typeJournal article
dc.type.dcmiText
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