Rapid Scheduling of Efficient FPGA Architectures for Next-Generation HSDPA Wireless System Using Precision C Synthesizer

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dc.citation.bibtexNameinproceedingsen_US
dc.citation.conferenceNameIEEE International Workshop on Rapid Systems Prototypingen_US
dc.citation.firstpage179
dc.citation.lastpage185
dc.citation.locationSan Diego, CA,en_US
dc.contributor.authorGuo, Yuanbinen_US
dc.contributor.authorMcCain, Dennisen_US
dc.contributor.authorXu, Gangen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)en_US
dc.date.accessioned2007-10-31T00:45:45Z
dc.date.available2007-10-31T00:45:45Z
dc.date.issued2003-06-20
dc.date.modified2003-12-02en_US
dc.date.note2003-07-11en_US
dc.date.submitted2003-06-20en_US
dc.descriptionConference Paperen_US
dc.description.abstractIn this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architec-tures are scheduled rapidly with specific hardware re-source/timing/architecture constraints from C/C++ level modeling by allocating the usage of functional units and real-time requirements. Using this methodology, a system-on-chip architecture for the next-generation CDMA system, i.e., HSDPA system, is prototyped rapidly. Advanced algo-rithms including chip-level equalizer, turbo codec and clock tracking, frequency offset compensation, are scheduled with Precesion C. A relatively more area/timing efficient RTL architecture is generated automatically and integrated with other design blocks in HDL designer, then implemented efficiently in Xilinx FPGAs. This new design flow demon-strates productivity improvement of 2X for typical wireless communication algorithms and reduces the risk of product development dramatically.en_US
dc.description.sponsorshipNokiaen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.description.sponsorshipNational Science Foundationen_US
dc.identifier.citationY. Guo, D. McCain, G. Xu and J. R. Cavallaro, "Rapid Scheduling of Efficient FPGA Architectures for Next-Generation HSDPA Wireless System Using Precision C Synthesizer," 2003.
dc.identifier.urihttps://hdl.handle.net/1911/19924
dc.language.isoeng
dc.subjectHSDPA*
dc.subjectFPGA architecture*
dc.subjectPrecision C*
dc.subjectRapid Scheduling*
dc.subject.keywordHSDPAen_US
dc.subject.keywordFPGA architectureen_US
dc.subject.keywordPrecision Cen_US
dc.subject.keywordRapid Schedulingen_US
dc.titleRapid Scheduling of Efficient FPGA Architectures for Next-Generation HSDPA Wireless System Using Precision C Synthesizeren_US
dc.typeConference paper
dc.type.dcmiText
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