This thesis describes the development of a SPICE sub-circuit model for an avalanche triggered SCR used for ESD protection in integrated circuits. The purpose of this work was to develop a model that accurately predicts the terminal characteristics of the SCR operating under steady state and transient conditions. Process and device simulations (using Technology Computer Aided Design tools, or TCAD tools) were used to gain insight into the dynamics of the complex SCR behavior prior to and during the latchup triggering. Test structures of the SCR, as well as its sub-components, were fabricated for characterization and modeling data collection. The TCAD results gave us access to internal physical quantities at key points along the I--V characteristics, which explicitly indicated the dynamics leading to latchup triggering. These analyses and the test structure characterization were necessary to properly formulate the SPICE model. The SPICE model development approach is presented, as well as methods to validate the model including steady state and fast rise time transient measurements on the actual ESD circuit. This is the first SPICE model presented for an avalanche triggered SCR demonstrating accurate terminal behavior under both steady state and transient triggering conditions. It is intended for use in a design environment for examining ESD circuit behavior at the chip level. The model allows a way to synthesize new circuits in a simulation environment without the need to fabricate test circuits and variations in silicon. Furthermore, the physical insight gained from the models will become more important as process technologies scale into deep submicron feature sizes.