Architectures for a CORDIC SVD Processor
| dc.citation.conferenceDate | 1986 | en_US |
| dc.citation.conferenceName | Real Time Signal Processing IX | en_US |
| dc.citation.firstpage | 45 | en_US |
| dc.citation.lastpage | 53 | en_US |
| dc.citation.location | San Diego, CA | en_US |
| dc.contributor.author | Cavallaro, Joseph R. | en_US |
| dc.contributor.author | Luk, Franklin T. | en_US |
| dc.date.accessioned | 2012-05-07T21:33:11Z | en_US |
| dc.date.available | 2012-05-07T21:33:11Z | en_US |
| dc.date.issued | 1986-08-21 | en_US |
| dc.description.abstract | Architectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (CORDIC) algorithms to diagonalize 2X2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation. | en_US |
| dc.description.sponsorship | Army Research Office | en_US |
| dc.description.sponsorship | Cornell University | en_US |
| dc.identifier.citation | J. R. Cavallaro and F. T. Luk, "Architectures for a CORDIC SVD Processor," 1986. | en_US |
| dc.identifier.uri | https://hdl.handle.net/1911/64042 | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | SPIE - The International Society for Optical Engineering | en_US |
| dc.subject | CORDIC | en_US |
| dc.subject | SVD | en_US |
| dc.subject | Symmetrization | en_US |
| dc.subject | Systolic Array Processor | en_US |
| dc.title | Architectures for a CORDIC SVD Processor | en_US |
| dc.type | Conference paper | en_US |
| dc.type.dcmi | Text | en_US |