Architectures for a CORDIC SVD Processor

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dc.citation.conferenceDate1986en_US
dc.citation.conferenceNameReal Time Signal Processing IXen_US
dc.citation.firstpage45
dc.citation.lastpage53
dc.citation.locationSan Diego, CAen_US
dc.contributor.authorCavallaro, Joseph R.
dc.contributor.authorLuk, Franklin T.
dc.date.accessioned2012-05-07T21:33:11Z
dc.date.available2012-05-07T21:33:11Z
dc.date.issued1986-08-21
dc.description.abstractArchitectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (CORDIC) algorithms to diagonalize 2X2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation.en_US
dc.description.sponsorshipArmy Research Officeen_US
dc.description.sponsorshipCornell Universityen_US
dc.identifier.citationJ. R. Cavallaro and F. T. Luk, "Architectures for a CORDIC SVD Processor," 1986.
dc.identifier.urihttps://hdl.handle.net/1911/64042
dc.language.isoengen
dc.publisherSPIE - The International Society for Optical Engineeringen_US
dc.subjectCORDICen_US
dc.subjectSVDen_US
dc.subjectSymmetrizationen_US
dc.subjectSystolic Array Processoren_US
dc.titleArchitectures for a CORDIC SVD Processoren_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
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