Hardware Security Primitives for Resource-Constrained Devices

dc.contributor.advisorYang, Kaiyuan
dc.creatorLi, Dai
dc.date.accessioned2021-08-16T19:41:22Z
dc.date.available2021-11-01T05:01:16Z
dc.date.created2021-05
dc.date.issued2021-08-13
dc.date.submittedMay 2021
dc.date.updated2021-08-16T19:41:22Z
dc.description.abstractWith the number of IoT devices surpassed global population, the shortage of energy, area and security of IoT presents a challenge to its application in wider scenarios. The issues of cyber security, information and privacy have been critical to the involvement of edge devices to industry, finance and personal life. Modern edge devices experience various attacks from different dimensions. In the physical domain, reverse-engineering, micro-probing and optical-reading are some widely used techniques to hack IC structure and data information. Trojan injection, side-channel analysis, web attacks are some popular way to carry out non-invasive attack. For resource-constrained devices, these attacks are especially efficient. There are mature solutions such as trusted platform module (TPM) and trusted execution environment (TEE) deployed by Intel and ARM to protect devices from some attacks. They provide key generation and storage, cryptography algorithms and other functions to ensure the confidentiality and integrity of device. But they come with issues of high area and energy budget for resource-constrained devices. Some algorithms they use such as RSA can be cracked by quantum computer easily. To provide better security for edge devices with affordable cost and robustness against prevalent attacks and quantum computers, we designed memory-centric hardware to accelerate the root and chain of trust of miniaturized area and energy. Three major projects were implemented to realize this concept. First, a 562-feature-square physically unclonable function provided state-of-the-art energy and area for secure key generation. Second, an 8-T CAM based network intrusion detection system performed signature-based intrusion detection for distributed IoT devices with 1.54-fJ/Byte/Search efficiency. The automata engine with system-level and circuit-level co-design presented the first silicon solution for IoT hardware firewall. Third, a processing-in-memory accelerator (PQC) for post-quantum cryptography was implemented to provide compact and low-power engine for PQC computation. A range-matching CAM-based cumulative-distribution-table (CDT) sampler was implemented to achieve 8pJ/sample energy efficiency and 100M sample/s throughput. A 6-T SRAM-based near-memory accelerator for number theoretical transformation was implemented for ultra-compact single-bank NTT operation for Ring-LWE cryptography. The use of in- and near-memory computation in security achieved area and energy efficiency compatible with low-power IoT applications.
dc.embargo.terms2021-11-01
dc.format.mimetypeapplication/pdf
dc.identifier.citationLi, Dai. "Hardware Security Primitives for Resource-Constrained Devices." (2021) Diss., Rice University. <a href="https://hdl.handle.net/1911/111210">https://hdl.handle.net/1911/111210</a>.
dc.identifier.urihttps://hdl.handle.net/1911/111210
dc.language.isoeng
dc.rightsCopyright is held by the author, unless otherwise indicated. Permission to reuse, publish, or reproduce the work beyond the bounds of fair use or other exemptions to copyright law must be obtained from the copyright holder.
dc.subjectHardware Security
dc.subjectVLSI
dc.subjectCryptography
dc.subjectKey
dc.subjectNetwork Intrusion Detection
dc.subjectProcessing-In-Memory
dc.titleHardware Security Primitives for Resource-Constrained Devices
dc.typeThesis
dc.type.materialText
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.disciplineEngineering
thesis.degree.grantorRice University
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy
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