Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbed

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dc.citation.conferenceDate2006en_US
dc.citation.conferenceName40th Asilomar Conference on Signals, Systems and Computersen_US
dc.citation.firstpage1161en_US
dc.citation.lastpage1165en_US
dc.citation.locationPacific Grove, CAen_US
dc.contributor.authorMyllylä, Markusen_US
dc.contributor.authorJuntti, Markkuen_US
dc.contributor.authorLimingoja, Mattien_US
dc.contributor.authorByman, Aaronen_US
dc.contributor.authorCavallaro, Joseph R.en_US
dc.contributor.orgCenter for Multimedia Communicationen_US
dc.date.accessioned2012-06-12T21:21:44Zen_US
dc.date.available2012-06-12T21:21:44Zen_US
dc.date.issued2006-11-01en_US
dc.description.abstractThe performance of two field programmable gate array (FPGA) implementations of a linear minimum mean square error (LMMSE) based detector is evaluated in real-time radio channels. Two square root free algorithms based on the QR decomposition (QRD) via Givens rotations, namely coordinate rotation digital computer (CORDIC) and squared Givens rotation (SGR) algorithms, are applied for the LMMSE detector implementation with pipelined systolic array architectures. The implementations are mapped to Elektrobit 2 x 2 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) hardware testbed for 4G MIMO systems (EB4G). The presented measurement results are done with a Propsim C8 MIMO channel emulator and compared to the simulated results.en_US
dc.description.sponsorshipElekrobiten_US
dc.description.sponsorshipNokia Networksen_US
dc.description.sponsorshipNokia Technology Platformsen_US
dc.description.sponsorshipTexas Instrumentsen_US
dc.description.sponsorshipFinnish Funding Agency for Technology and Innovationen_US
dc.description.sponsorshipTekesen_US
dc.identifier.citationM. Myllylä, M. Juntti, M. Limingoja, A. Byman and J. R. Cavallaro, "Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbed," 2006.en_US
dc.identifier.doihttp://dx.doi.org/10.1109/ACSSC.2006.354937en_US
dc.identifier.otherhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4176747en_US
dc.identifier.urihttps://hdl.handle.net/1911/64253en_US
dc.language.isoengen_US
dc.publisherIEEEen_US
dc.subjectFPGAen_US
dc.subjectLMMSEen_US
dc.subjectPipelined systolic array architectureen_US
dc.subjectMIMO-OFDMen_US
dc.titlePerformance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbeden_US
dc.typeConference paperen_US
dc.type.dcmiTexten_US
dc.type.dcmiTexten_US
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